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Altera pin assignment

  • Thread starter shaiko
  • Start date Jun 17, 2015
  • Jun 17, 2015

Advanced Member level 5

Hello, Altera's Quartus has 3 ways to assign pins to the FPGA device: 1. Assignment Editor. 2. Pin Planner. 3. Direct text input into *.QSF. My question: Are these tools synchronized with each other? For example: if I do initial assignments using the Pin Planner and then make changes in the *.QSF file - will the changes in the QSF propagate back to the Pin Planner settings?  

ads-ee

Super Moderator

As long as you save the changes to the QSF, I 'm pretty sure they get loaded for each tool (you may have to close and reopen the tool to get the latest changes), but I might be mis-remembering as it's been 5-6 years since I've used Quartus.  

TrickyDicky

Advanced member level 7.

Any changes you make via assignment editor and pin planner are written to the QSF file (stands for quartus settings file I think). Quartus uses the QSF file to set up the assignment editor and pin planner (and all the other stuff in its gui). Ensure you havent got the project open when you hand edit the .qsf though You can also assign pins via attributes in the HDL.  

TrickyDicky said: Ensure you havent got the project open when you hand edit the .qsf though Click to expand...

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How to assign pins in Quartus II

We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to Quartus II.

In particular, I am looking for a way to explicityly assign pins to the chip I am using. In Xilinx, I'd edit the netlist file but I can find no such thing in Quartus. There is a program (Assignments => Pin Planner) that does this, but it has a clunky GUI and I'd far prefer to edit the pins in a text editor, so my twofold question is

A: How do I find the file that stores the pin assignment? It's not listed under my files in the project navigator but the pins I've assigned in Pin Planner stay from session to session so they must be stored somewhere .

B: Is this a horrible idea?

IDE is Quartus II 10.1 Development kit is MAX II Development Board Language is VHDL

EDIT: Right now, I've run into the problem that I'm trying to interface with the Dev Kit through USB. I'm making a serial data receiver on it and have given it a Data In pin. The Dev Kit has a USB receiver so I'm trying to map din to whichever pin the USB connector is on. According to a file I have (rm_maxII-develop_board-rev1.pdf) the USB connector is on "Board Designation U13" but when I go into the Pin PLanner and try to assign that, there is no PIN_U13. I suspect this is an error in the pdf, rather than in Pin Planner but seing as I've never worked with Altera products before, I'm very confused.

Qiu's user avatar

  • Ah, you posted here too. :-) I added answer at overmapped.com/questions/how-to-assign-pins-in-quartus-ii –  Prof. Falken Commented Apr 11, 2011 at 14:29
  • I did - slightly before I read about Overmapped and figured that'd be a better place for it. What's your user name on Overmapped? I see no replies from Amigable Clark Kant over there. –  shieldfoss Commented Apr 12, 2011 at 9:14
  • Jakob. It's here too if you look around hard enough. :-) –  Prof. Falken Commented Apr 12, 2011 at 9:26

A) You need to edit the *.qsf file, and add lines similar to the following:

B) While I will sometimes use the pin planner in the early stages of a design, I almost exclusively edit the qsf file directly when modifying pins, adding or removing VHDL files from the design, etc. To be completely safe, when making large changes (particularly to optimization or compiler settings) I will make sure Quartus is not running. I've been working this way with Quartus since it came out, and have not had any problems.

Once your design is compiled, you can refer to the *.pin file to see the final pinout for the FPGA. In particular, refer to the column indicating whether or not the pin is manually assigned, as any pins not specifically assigned to a location will change pretty much every time you recompile the chip (which is sub-optimal if you've already made a PCB! :).

Charles Steinkuehler's user avatar

  • @medivh, that I don't know, please tell us where you found it. –  Prof. Falken Commented Apr 13, 2011 at 10:04

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Pin assignments do not appear to be assigning in bdf - Quartus 17.1

Following the pin assignment diagram in the device manual for my Max 10 DE10-Lite, I assigned all the correct pins to their associated inputs and outputs as seen below:

pin assignments

However, when I go back to my bdf file and run the full compile, the pin assignments do not appear, as they have in the past.

bdf file

I thought to myself, maybe they just aren't showing up, but they are actually still assigned. So I programmed my board, and it simply remains black, with my circuit not working at all. Has anyone seen this before? I have tried creating a new project, and still nothing.

  • troubleshooting

Tess Christensen's user avatar

  • \$\begingroup\$ Not an answer because I'm no Quartus expert, but a hint: Under the GUI, there is likely to be a command line interface, with ways of showing (console, or log files) how the actual compilation commands operate, and what their arguments (constraint file names etc) are. Looking at those files, you may be able to trace the pin assignments and see where they go missing. \$\endgroup\$ –  user16324 Commented Jan 18, 2020 at 13:36
  • \$\begingroup\$ @BrianDrummond Yes, if you check the .QSF file in the project files, that'll be a plaintext file with all of the configurations as commands like you said. \$\endgroup\$ –  Charles Clayton Commented Jan 19, 2020 at 17:41

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altera qsf pin assignment

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COMMENTS

  1. QSF Assignments

    Table 5.QSF Assignments. The input/output termination assignment specifies the termination value in ohm on the pin in question. To enable the series/parallel termination ports, include these assignments, which specify the series and parallel termination values for the pins.

  2. PDF AlteraQuartus Prime Standard Edition Settings File Reference Manual

    Specifies the Electronic Board Description (EBD) file that contains the path description for an I/O pin. Type. String. Device Support. This setting can be used in projects targeting any Altera device family. Notes. This assignment supports wildcards. The value of this assignment is case sensitive. Syntax

  3. Altera® Quartus® Prime Standard Edition Settings File ...

    Altera® Quartus® Prime Standard Edition Settings File Reference Manual. 1. Altera® Quartus® Prime Standard Edition Settings File Reference Manual x. 1.1. Advanced I/O Timing Assignments1.2. Analysis & Synthesis Assignments1.3. Assembler Assignments1.4. Assignment Group Assignments1.5. Classic Timing Assignments1.6.

  4. Specify exact pin locations on FPGA

    I haven't worked with Altera, but in Xilinx you could manually specify pin assignments before the compile in the constraints file (.UCF for Xilinx). From what I can tell, you can do the same thing for Altera in the Quartus II .QSF file by using set_location_assignment. See the example .QSF file on page 6 in this Quartus II Handbook.

  5. PDF DE2-115 PIN ASSIGNMENTS

    DE2-115 Board I/O Pin Assignments: Switches, LEDs, and 7-Segment Displays. Table 1: Pin assignments for slide switches. Table 2: Pin assignments for pushbutton (debounced) switches. Table 3: Pin assignments for LEDs. Table 4: Pin assignments for 7-segment displays. Table 5: Pin assignments for clock inputs.

  6. How to include a QSF file with the Pin Assignments into the main QSF

    You can call assignments from other Quartus® Prime Settings Files using the source keyword and the Quartus® Prime Settings File name you want to call. Using the source keyword allows you to use assignments from any other Quartus® Prime Settings File without having to import the assignments or transfer them to the current Quartus® Prime ...

  7. Assigning pins in DE2 115

    2,645 Views. Start an Analysis and Synthesis process, so that Quartus automatically collects the I/O pins from your project. Then, go to the Quartus Assignments menu and select Pins. You are presented with the list of the I/Os and you simply assign each of them the desired fpga pin. Refer to DE2 115 schematic to find out what fgpa pins are ...

  8. Altera pin assignment

    Hello, Altera's Quartus has 3 ways to assign pins to the FPGA device: 1. Assignment Editor. 2. Pin Planner. 3. Direct text input into *.QSF. My question: Are these tools synchronized with each other? For example: if I do initial assignments using the Pin Planner and then make changes in...

  9. How do I fix pin assignments on a Quartus Prime Lite project?

    I deleted the .qsf file from the project directory (through the file system). I selected Assignments > Import Assignments and imported DE1_SoC.qsf. When I open the assignment editor, the pins to which I had assigned nodes show up with question marks in their status column: In the bottom of the assignment editor, I see my earlier pin assignments:

  10. DESL: QSF

    DESL: Quartus II settings file with Pin Assignments. The purpose of this menu is to download the .qsf file from the Altera web site. go to the QSF Intel Home Page web page. QSF home page. Select DE1-SoC, scroll to the bottom of the page. Right click QSF, save file to your computer. Import this file into your Quartus program to assign all the ...

  11. 2.2.3. Assigning Differential Pins

    Assigning Differential Pins. 2.2.3. Assigning Differential Pins. When you assign a differential I/O standard to a single-ended top-level pin in your design, the Pin Planner automatically recognizes the negative pin as part of the differential pin pair assignment and creates the negative pin for you. The Intel® Quartus® Prime software writes ...

  12. vhdl

    8. A) You need to edit the *.qsf file, and add lines similar to the following: set_location_assignment PIN_AP30 -to qdr_q[35] B) While I will sometimes use the pin planner in the early stages of a design, I almost exclusively edit the qsf file directly when modifying pins, adding or removing VHDL files from the design, etc.

  13. How to assign different pins in Pin Planner in Quartus?

    \$\begingroup\$ As a start, look in the project's .qsf (Quartus Settings File). That will list the pin physical constraints including pin locations. You can edit and save that directly, following the format of the existing pin location constraints, which should be there from what you show. Then try synthesizing that and let us know. \$\endgroup\$

  14. PDF How to Import Pin Assignments

    "defaultPinAssignments.qsf" pin assignment file is simply to create a safe sandbox for the Out of the Box MAX V Development Board without the worry of accidently assigning pins already allocated to the onboard devices such as the flash and USB peripherals.

  15. Solved: Master qsf file

    Master qsf file. 09-30-2022 09:49 AM. Hello forum, I am new to the Quartus software. I have written the code and it is working fine. I had to interface the Altera Cyclone 4 EP4CE22F17C6N.

  16. Quartus Prime Settings File (.qsf) Definition

    Prime. Settings File (.qsf) Definition. The Quartus® Prime Settings File ( .qsf) contains all of the project-wide and entity-level assignments and settings for the current revision of the project. A separate Quartus® Prime Settings File exists for each individual revision. The Quartus® Prime Settings File syntax is based on Tcl script syntax.

  17. PDF Table 2: Pin assignments for slide switches

    DE2-115 Board I/O Pin Assignments: Switches, LEDs, and 7-Segment Displays Table 1: Daughter Board Pin assignments Signal Name FPGA Pin No. Description SW3_DB PIN_AB22 Rocker Switch[3] SW2_DB PIN_AB21 Rocker Switch[2] SW1_DB PIN_AC21 Rocker Switch[1] SW0_DB PIN_AD21 Rocker Switch[0] KEY1_DB PIN_AC19 Push-button[1]

  18. fpga

    I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin assignments on my qsf file. That being said, I don't know where to find the correct pins and how I would assign them to the inputs and outputs of my module. The model I am using is a 10CL025YU256I7G. fpga. pins. intel-fpga. quartus. Share.

  19. 3.2.1. Generating Pin Assignment Files

    The Intel® Quartus® Prime-generated .pin contains the I/O pin name, number, location, direction, and I/O standard for all used and unused pins in the design. Click Assignments > Pin Planner to modify I/O pin assignments. You cannot import pin assignment changes from a Mentor Graphics* .pin into the Intel® Quartus® Prime software.. The .fx is an input or output of either the Intel® Quartus ...

  20. fpga

    set_location_assignment PIN_C204 -to reset. set_location_assignment PIN_R138 -to LED. When I compile the code, I get the following error: Info (21077): Low junction temperature is -40 degrees C. Info (21077): High junction temperature is 100 degrees C.

  21. FPGA Boards for the Intel® FPGA Academic Program

    Intel® Quartus® Prime Design Software Setting File with Pin Assignments: QSF: Intel® Quartus® Software Synopsis Design Constraints: SDC . DE10-Standard. The DE10-Standard board has the same feature set as the DE1-SoC board but with some enhancements: a larger FPGA, more memory, an HSMC high-speed connector, and black & light mini LCD. It's ...

  22. Altera FPGA I/O weak pull ups

    There are two ways of doing it. 1. Pin Planner. The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project open, go to the Assignments menu and select Pin Planner (or press Ctrl + Shift + N ). In the pin planner window, in the All pins view at the bottom ...

  23. Pin assignments do not appear to be assigning in bdf

    Following the pin assignment diagram in the device manual for my Max 10 DE10-Lite, I assigned all the correct pins to their associated inputs and outputs as seen below: ... if you check the .QSF file in the project files, that'll be a plaintext file with all of the configurations as commands like you said. \$\endgroup\$