make pin assignments

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Specify exact pin locations on FPGA

I have an Altera Cyclone IV FPGA, and I use the Quartus II software as the compiler.

In the "PinPlanner" it is possible to specify groups of pins (e.g. data buses). For each group, an I/O bank and an I/O standard (e.g. LVDS) can be specified. Then, the fitter (place and route) provides specific "Fitter Locations", specifying a precise pin for each individual wire.

Is there a way to specify the precise pin locations before the fitter attempts to fit the pins within each bank for me? Can this be done in the Pin lanner?

2 Answers 2

There are two ways of specifying PIN assignment — you can either use PinPlanner or set_location_assignment to specify the PIN along with set_instance_assignment to specify the IO standard.

I recommend you read I/O Management documentation from Altera. But here are few examples:

These are location assignments for 1 GbE RGMII Ethernet Interface:

And here is an LVDS clock input to FPGA:

Hope it helps. Good Luck!

• \$\begingroup\$ Thanks. You give examples of using set_location_assignment , but how can this be done using the PinPlanner? \$\endgroup\$ –  Randomblue Commented Sep 18, 2012 at 16:02
• \$\begingroup\$ @Randomblue: Have you seen the doc? In PinPlanner, there will be a grid of top-level ports with pin location, I/O standard, etc. Just click, select values from drop-down, and that's it. \$\endgroup\$ –  user8459 Commented Sep 18, 2012 at 16:26
• \$\begingroup\$ Aha, well my problem is that there is no "Location" column, just a "Fitter location" column that is populated after the Fitter has been run. \$\endgroup\$ –  Randomblue Commented Sep 18, 2012 at 16:31
• \$\begingroup\$ @Randomblue: Are you sure you are in Pin Planner? You should see something like this — idle-logic.com/wp-content/uploads/2011/12/PinPlanner.png There is no Fitter location, that sounds more like a place & route... \$\endgroup\$ –  user8459 Commented Sep 18, 2012 at 16:33

I haven't worked with Altera, but in Xilinx you could manually specify pin assignments before the compile in the constraints file (.UCF for Xilinx).

From what I can tell, you can do the same thing for Altera in the Quartus II .QSF file by using set_location_assignment .

See the example .QSF file on page 6 in this Quartus II Handbook .

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QII52013-9.1.0 Introduction 5. I/O Management The process of managing I/Os for FPGA devices involves more than just fitting design pins into a package. The increasing complexity of I/O standards and pin placement guidelines are just some of <strong>the</strong> factors that influence pin-related assignments. Both I/O capabilities of <strong>the</strong> FPGA device and board layout guidelines influence pin location and o<strong>the</strong>r types of assignments. Therefore, it is necessary to begin I/O planning and PCB development even before starting <strong>the</strong> FPGA design. Altera provides many resources for I/O planning. This chapter provides information on how to make pin assignments, how to enter I/O interface information in <strong>the</strong> <strong>Pin</strong> <strong>Planner</strong>, how to create I/O-based top-level HDL files, how to validate your pin assignments, and how to generate a valid pin-out file for use with third-party PCB tools. You can consult <strong>the</strong> device-specific pin connection guidelines available on <strong>the</strong> Altera ® website for your board layout. You can also benefit from <strong>the</strong> <strong>Pin</strong> Advisors available in <strong>the</strong> Quartus II software. f To get updated information about <strong>the</strong> Altera resources available for I/O planning, refer to <strong>the</strong> I/O Managment, Board Development Support, and Signal Integrity Analysis Resource Center on <strong>the</strong> Altera website. f For guidelines about PCB designs for Altera high-speed FPGAs, refer to AN 315: Guidelines for Designing High-Speed FPGA PCBs, and <strong>the</strong> Board Design Resource Center on <strong>the</strong> Altera website. This chapter includes <strong>the</strong> following topics: ■ “Understanding Altera FPGA <strong>Pin</strong> Terminology” on page 5–2 ■ “I/O Planning Overview” on page 5–5 ■ “Device Selection” on page 5–7 ■ “Early I/O Planning <strong>Using</strong> <strong>the</strong> <strong>Pin</strong> <strong>Planner</strong>” on page 5–7 ■ “Importing and Exporting <strong>Pin</strong> <strong>Assignments</strong>” on page 5–12 ■ “<strong>Creating</strong> <strong>Pin</strong>-Related <strong>Assignments</strong>” on page 5–13 ■ “<strong>Creating</strong> <strong>Pin</strong> <strong>Assignments</strong> <strong>Using</strong> <strong>the</strong> <strong>Pin</strong> <strong>Planner</strong>” on page 5–14 ■ “<strong>Creating</strong> <strong>Pin</strong> <strong>Assignments</strong> with Tcl” on page 5–21 ■ “<strong>Creating</strong> <strong>Pin</strong> <strong>Assignments</strong> with <strong>the</strong> Chip <strong>Planner</strong>” on page 5–22 ■ “<strong>Creating</strong> <strong>Pin</strong> <strong>Assignments</strong> in HDL” on page 5–22 ■ “<strong>Creating</strong> <strong>Pin</strong> <strong>Assignments</strong> with Low-Level I/O Primitives” on page 5–24 ■ “Validating <strong>Pin</strong> <strong>Assignments</strong>” on page 5–24 ■ “Validating <strong>Pin</strong> <strong>Assignments</strong> after Full Compilation” on page 5–39 ■ “I/O Timing Analysis” on page 5–40 © November 2009 Altera Corporation Quartus II Handbook Version 9.1 Volume 2: Design Implementation and Optimization

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Pin Assignments

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Making pin assignments

Go to the "Assignments" menu and select "Import Assignments...". Import the  de0-nano/rgbmatrix-fpga.qsf  file. After you do this, a message should appear in the "System" console tab at the bottom of Quartus: "Import completed. 14 assignments were written (of of 14 read)."

This guide was first published on Jul 29, 2012. It was last updated on Mar 08, 2024.

This page (Pin Assignments) was last updated on Jul 12, 2012.

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Pin assignments

This section describes the pin assignment and the pin functions.

This device provides flexibility when it comes to routing and configuration of the GPIO pins. However, some pins have recommendations for how the pin should be configured or what it should be used for.

In addition to the information in the pinout tables for the respective packages, the following peripherals have dedicated pins that should be used for proper operation:

• TWI - For the fastest TWI 1 Mbps mode, the two high-speed TWI pins must be configured in the TWI peripheral's PSEL registers, and the 20 mA open drain driver enabled using the E0E1 drive setting in the DRIVE field of the PIN_CNF GPIO register.
• QSPI - For QSPI only the dedicated GPIO pins from the following table shall be used. These must be enabled using the Peripheral option of the PIN_CNF[p].MCUSEL register. The GPIO must use the high drive H0H1 configuration in the DRIVE field of the PIN_CNF GPIO register.
• SPIM4 - For the 32 Mbps SPI mode, the special purpose GPIO pins are enabled using the Peripheral option of the PIN_CNF[p].MCUSEL register. When activated, the SPIM PSEL settings are ignored, and the dedicated pins are used. The GPIO must use the high drive H0H1 configuration in the DRIVE field of the PIN_CNF GPIO register.
• TRACE - When using trace, the TRACEDATA[n] and TRACECLK GPIO pins must all use the extra high drive E0E1 configuration in the DRIVE field of the PIN_CNF GPIO register. Also, the TND option of the PIN_CNF[p].MCUSEL register must be used.

For all high-speed signals, the printed circuit board (PCB) layout must ensure that connections are made using short PCB traces. Refer to the manufacturer's PCB design recommendations for additional information.

aQFN94 pin assignments

The aQFN94 package has 94 pins in addition to four corner pads and a die pad.

WLCSP pin assignments

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• Common Ground: Seeking Pin Assignment Balance in FPGA-Based Boards

Component placement ignored (bad layout)

Component placement considered (good layout)

DDR3 and QDR II SRAM, FPGA tool-derived pin assignments

One board in a large ASIC prototyping system

Using FPGA knowledge to guide the PCB pin-swapping process

Predicting that IC density and complexity will continue to increase is kind of like predicting that the sun will come up in the morning-you'd literally have to be living under a rock to not be aware of this. And so it is with FPGAs, which are getting more, not less, complex; whose pin counts are going up, not down; and for which the available silicon seems to grow faster than many engineers can figure out how to use it. The only thing that steadfastly refuses to change is design schedules, which bewilderingly remain as constant as the sun.

Integrating these ever-more complicated devices into their host PCBs has proven to be extraordinarily challenging. FPGA designers, schematic engineers, and PCB designers find themselves locked in a divergent battle, struggling to create device pin assignments that satisfy both the FPGA and the PCB. Traditional tools almost encourage each specialist to "throw the design over the wall." As the design progresses, this tool-mandated "not my job" mentality dooms the team to wasting precious time, often late in the project, iterating between the FPGA and PCB design, searching in vain for common ground in pin assignments.

Regrettably, it's the PCB that usually suffers, with more layers and vias being added to accommodate the FPGA. To make matters worse, this typically manual round-trip process introduces errors that may not be exposed until the first prototype is powered up in the lab.

All's Well That Starts Well

Take an average FPGA-based PCB design containing two or three FPGAs. Most processes let the FPGA designer have all of the pin assignment fun (as in ,"It's fun to hit my thumb with a hammer"), using the FPGA tools, scripts, text files, spreadsheets, home-grown utilities, and whatever other tricks are at his/her disposal. Those pin assignments are then passed to the schematic engineer who gets the fun (see above for the definition of "fun") of creating symbols and wiring up the schematic using precisely the same pins as the FPGA designer, including all of the power pins that can number in the hundreds. Not to mention the lingering fear lurking in the back of his/her mind that if anything is misconnected, the system won't work. Or even worse, on first power up the prototype will do nothing more than radiate lots of heat until it melts into a useless pile of expensive FPGAs and fiberglass.

And this doesn't even begin to address the PCB designer, that poor soul at the bottom of the design food chain who just happens to have had all of his/her allotted time chewed up by everyone else, who has little say in the design process, and whois told to "fix it but don't change anything" on a board where the PCB routing was never considered for a fleeting µ-second!

That this situation sets the stage for a lot of hand wringing, late nights, finger pointing, heated battles, and endless loops through the flow-usually at the end of the design cycle, when it can least be afforded-is only too predictable. Oh, and don't forget that all FPGA pin assignment changes have to propagate through the entire flow, every time, with flawless accuracy.

This, with a little embellishment, is what happens with manyaverage FPGA-based boards. Just imagine ASIC prototyping designs, which can contain dozens of FPGAs. The problems listed above become practically unmanageable, and it is a testament to the engineers'-and PCB designers'-skill that any of these prototyping systems are ever made to work correctly in a time frame that ensures the ASIC is taped out before the market renders it obsolete.

Take the following two screenshots ( Fig. 1 and Fig. 2 ), which are admittedly an exaggeration but nevertheless highlight what can happen while picking pins if component placement is either ignored (bad) or considered (good):

Assuming both designs satisfy the needs of the FPGA (the large device in the middle), which one would most likely inspire the PCB designer to request an unpleasant chit-chat with engineering? True, only the rat's nests are represented here. But their implication is clear: the tangled mass of connections scattered across the FPGA in Figure 1 are destined to cause a routing nightmare. To understand the roots of this issue, you need to look no further than the techniques that are generally deployed, and the data that is normally acknowledged, during the FPGA pin assignment process.

Article Sections

• The Heart of the Matter \\[Next\\]
• Look At It From My Perspective

Wait Just a Minute

• The Heart of the Matter

Regardless of how FPGA I/O pins are selected (automatically, manually, or a combination of the two), if the pin assignments have any hope of working well for the entire system, three factors must be considered-and these must be considered by the designer and any tools used in the process:

• The usage rules of the FPGA. In other words, what are the pins and the underlying silicon capable of, and how does one set of pin assignments affect subsequent pin assignments? (This could be a topic for another article addressing the nonsensical idea that it's possible to efficiently shoehorn a staticswap matrix into the PCB-driven FPGA pin-swapping process.)
• The characteristics of the signals in the design. Not all signals are created equal. A DDR3 DIMM byte lane, for example, typically contains 8 data bits, a mask bit, and a set of differential strobes. Arbitrarily assigning the data and strobes to random locations on the FPGA is almost guaranteed to fail. The FPGA design tools know this. The FPGA designer knows this. And any tool that assists in the pin assignment process has to know this. This is a perfect example of why a PCB designer, swapping and moving signals based on the rules contained in a static swap matrix, is playing with fire.
• The placement of the components on the board. Of the three constraints, this is the one that has the biggest effect on the PCB routing. To pick pin assignments while ignoring the board-level component placement is like driving in the dark without headlights: after a few crashes, you'll get somewhere but probably nowhere close to where you want to be. This is also the one constraint that FPGA design tools do not natively or electronically comprehend because they focus on the FPGA - one FPGA. That's not to say that an FPGA designer can't successfully guide the FPGA tools based on his/her knowledge of the PCB component locations. But doing that across multiple FPGAs and then managing the pin assignment changes with each modification to the part placement is like a recurring bad dream.

An additional factor that is often disregarded but that needs to be addressed is the link between the FPGA and the schematics. Getting the FPGA connectivity captured in the schematic wouldn't be too painful if it were done only once. But that never happens. In fact, the connectivity changes constantly and radiates from two main sources: the FPGA designer, optimizing the pin outs for performance reasons, and the PCB designer, trying to reduce layer counts or routing time. As far as the hardware engineer is concerned, the source of the change is irrelevant-the FPGA connectivity still has to be updated accurately and reflected in the schematics.

Since the classic FPGA vendor tools already deal with the first two constraints mentioned above, it's the third one that any new tools or techniques need to focus on if the goal really is system-optimized pin assignments that work well for the FPGA and the board.

• Look At It From My Perspective \\[Next\\]

Before jumping to the conclusion that the easy answer is just to force FPGA designers to think outside the FPGA box, look at the problem from their perspective. Tasked with writing, simulating, and synthesizing the RTL; deliberating over the timing (both inside and outside the FPGA); selecting the proper I/O standards; assessing routing and clocking resources; sizing the I/O buffers;floorplanning the device; and, generating the programming files, FPGA designers have their own set of headaches to contend with. Throwing PCB routing into the mix does not help.

And for some sections of the design, FPGA designers may not have much say in the matter-for the FPGA to work, they could be forced (or at least implored) to use pin assignments derived algorithmically by the FPGA tools. These tools can assist the designer in interfacing the FPGA to DDR3s, QDR II+ SRAMs, RLDRAMs, etc. (Fig. 3) , and in producing soft IP cores. Testing an FPGA designer's patience then entails nothing more than proposing modifications to these hard- fought, "golden" pin assignments.

There are a multitude of other pin allocation decisions that can elicit thoughts of "What are they thinking?!" from those not intimately familiar with the FPGA's requirements, but that make perfect sense to FPGA designers. Some devices, for example, contain hard cores carefully constructed to communicate with specific types of external logic such as DSPs or Ethernet PHYs, and the silicon that implements that logic prefers certain I/O pins. So when FPGA designers rigidly insist that pin assignments are fixed, many times they're absolutely right.

So what happens when all of this makes its way to the board? This is where the pin assignment rubber meets the PCB routing road. It's at this point that the team is given its first real glimpse of how early design-cycle choices will actually affect the physical system. Signal integrity, mechanical and thermal qualities, manufacturing cost, packaging, reliability, power delivery and consumption-all the things whose effects and tradeoffs have been carefully evaluated throughout the design process-now begin to come together and their interactions play out.

High-speed components like DDR3 have not only stringent FPGA integration requirements but rigorous PCB requirements as well: distances between parts, maximum allowed signal length, number of layers and vias, crosstalk, etc. For each of the 240 nets on every DDR3 (and of course for every part), the PCB designer has to group the nets into bundles, merge those bundles onto their appropriate layers, and then flowplan and route them around any impeding obstructions-all with an eye toward meeting multiple, often conflicting, design objectives. Poorly chosen FPGA pin locations can turn this process into a veritable nightmare, resulting in round after round of impassioned team-wide negotiations that inevitably push the project's timeline right to its unforgiving edge. Worse, it can add layers to the PCB, which drives up the end product costs.

• Now What? \\[Next\\]

Any tools that claim to improve this situation have to be conversant in multiple design-space languages. They also have to be able to integrate, or at least easily communicate, with a range of other products, databases, and file formats. And as much as engineers enjoy deriding the EDA industry, EDA companies have developed new tools and flows to help design teams cope with integrating FPGAs onto PCBs.

Each of these products approach the problem in unique ways, but the bottom line is that all of them exploit component placement as a constraint in establishing FPGA pin assignments that complement the entire design, not just the FPGA. And all of them have been used effectively by engineers across the globe to reduce design cycles and increase product quality. However, first-generation tools have some limitations. They may require that PCB placement be done first, which implies that un-optimized (manual) pin assignment is also done first. Or, FPGA pin assignment rules may be missing in the PCB layout space, so that pin assignment is done manually.

A more advanced approach would assemble the FPGA rules, signaling, and part placement data (the 3 constraints listed above) into one location and then, through a "connectivity intent definition" mechanism, utilize I/O synthesis technology to automatically select the best FPGA pins across the entire design. Because the tool asks the designer to supply the connectivity intent instead of the actual pin assignments, the designer enjoys the luxury of knowing that no matter where the components are placed or oriented, the actual connectivity can be re-established by simply re-running synthesis. (Moving or rotating components implies a change only to the actual connectivity, not the connectivity intent.)

Cadence Allegro FPGA System Planner takes just such a "connectivity intent" approach. One customer was able to take full advantage of this capability when, at the last minute, it was discovered that an FPGA had to be flipped to the opposite side of the board. Using the "connectivity intent with synthesis" functionality, days of re-work was trimmed to a few hours. Another customerproduced a 48-FPGA ASIC prototyping system in half the time of their previous 15-FPGA single-board system (Fig. 4) .

• Wait Just a Minute \\[Next\\]

However, as with any product, FPGA pin planning tools are not a panacea. They will not, nor are they intended to, replace the FPGA vendor's tools. They can use, and ideally improve, pin assignments selected by the vendor tools-but in some designs, or for a host of other reasons, engineers may want to use existing FPGAtool-defined I/O locations. Again, because the FPGA tools cannot spell "PCB," these pin assignments are often not optimal, at least for the board.

In these circumstances the EDA tools, just like a machete or a screwdriver or a chainsaw, have to be used as they were intended to be, in the right place and at the right time in the design process. As such, any sufficiently advanced FPGA-PCB planning tool must be able to optimize, or guide the engineer in optimizing, FPGAtool-defined pin locations within an FPGA-constrained boundary, using algorithms that understand and adhere to the original, vendor-driven pin assignment rules.

There are other restrictions that these tools suffer from as well: they all view the PCB as a two-dimensional object and the routing as a point-to-point Manhattan connection, neither of which is true. (How drastically these assumptions affect I/O assignment quality is directly related to the PCB topology.) But perceiving the PCB to be two dimensional is certainly a lot better than not perceiving the PCB at all. Worse, some of these products, in some cases, view the FPGA as a fixed-pin device, which spawns a rash of problems downstream when swapping pins in the PCB.

An FPGA is a programmable device. By their very design, an FPGA's pins are dynamic-how one is used immediately and directly affects the others. This cannot be determined or orchestrated through a simple mechanism like a static swap matrix, which has none of this intelligence.Created too coarsely, a swap matrix will allow PCB designers to screw up the FPGA drastically. Too fine and they will be hamstrung, unable to swap anything of any significance.

One way to get beyond this would be to instill FPGA expertise into the PCB tool, perhaps through an underlying "engine," to lead the PCB designer in the right direction by suggesting FPGA-compliant pin swap candidates. Bringing FPGA awareness to the PCB designer's desktop would help ensure that they are continually steered toward a more predictable (and routable) solution (Fig. 5) . So it's not a single tool, but how well the tool flow understands FPGA-based designs that ultimately determines the team's fate and their ability to realize the completed system.

With better FPGA design-in tools that communicate in several languages (FPGA, schematic, and PCB), FPGA design-in can be a faster, less frustrating endeavor. But to properly solve the problems touched on in this article, these tools are going to have to take responsibility for their long-standing inability to adequately endorse the PCB-up front. Tools (and processes) that do not will continue to subject the entire team to a series of time-consuming, exasperating iterations, forcing the team to choose between the lesser of two evils: slip the schedule to allow for more iterations, or increase PCB layer counts (and potentially decrease system performance) to account for inferior FPGA pin assignments.

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Alternate pin assignment

I have notice a (probably) new feature: alternate pin assignment. I have created a new device and noticed that there is an “alternate pin assignments” tab when I open the symbol properties. Then I thought I have to add the alternate pin definitions when creating the symbol. Back to the symbol editor, I noticed that it’s possible for every pin to add alternate defintions, and I tried to do it. Example: Pin 1 was defined as P6.4 / A4. Port IO or analog input. So I left P6.4 as default and added A4 for alternate. Saved, updated in the schematic editor. Now when I open the symbol properdies, I was expecting to see P6.2 on the base name column, and A4 as an alternate, but it didn’t change. Here are a few questions:

• Did I miss one (a few) step(s)?
• In symbol properties, Alternate Assignment has only one column. What will happen if there is more than one alternate assignments? Example: pin 76 is P10.0 or UCB3STE or UCA3CLK.

Thanks for any hint!

I haven’t investigated this feature but could you be misinterpreting the purpose? Could it be for representing devices that come in say 40 pin DIP and 44 pin TQFP?

@retiredfeline It is just to assign alternate pin texts. Comes in handy for e.g. MCUs, where a pin can be GPIO/UART/SPI/Analog5, you get it. You can choose which pin name you want displayed. [EDIT] Electrical type and graphical style change as well

There will be a dropdown list with the alternates available. Initially, you see an empty field. Only after clicking it does the dropdown list appear.

It’s there since 6.0 .

Thanks, that’s exactly what I expected. Instead of displaying up to 5 ~ 6 different options, it would be a lot better to display tje pin I’m actually using, for instance only UART_TX as in your example. And I would also like to add an NC option.

Anyway I must be missing something. I configured it my lib and it doesn’t reflect in the schematic even if I update the lib.

Now in the schematic I had started, if I update the library, I can be sure that it has actually been upgraded since the corner pin 1 is now P6.4, and the A4 has disappeared.

Now my problem is: how can I do in the schematic to show the alternate pin name, A4 only?

Thanks for any hint.

Update: I found the trick!

Oopsy Daisy, I never realized that…

You are mis-using or mis interpreting the feature. It’s not used for all schematic symbols. KiCad’s libraries are a bit behind. The intention is that all sensible pin names are pre-defined in the library, and you choose one of the names for use in your schematic. To see how it works put one of the STM32 IC’s on your schematic, and then edit it’s properties. Then you can select a name from the Alternate Pin Assignments tab page.

This seems to work quite nicely for microcontrollers and other IC’s that have a limited number of pre-defined functions per pin. It does not work for FPGA’s or PLD’s where pins can be “anything”. But I don’t see much room for improvement there, except for just improving the symbol editor itself. It’s easy enough to pop a symbol into the symbol editor and change pin texts to your liking. And having a pre-defined symbol already defines the power pins, maybe clock and other dedicated pins and just leaves the I/O pins to change for you.

For me it seems finally a problem for the database approach. Pin names (and pin numbers) should be possible to override either from database or manually by schematic entry. Swapping rules should be either connected to in number or pin name or any new identifier therefore.

I don’t think so. By the way, my post above was maybe a bit confusing with the latest picture showing a chip with only pin 1 using this feature. I’m in the process of changing them all, but it takes time. With, say, 3 different configs for each pin in an average, it means 300 editions for this QFP100. Beside this, since it’s now able to define not only the alternate pin name, but also its nature (input / output / bidirectional, etc…), I think Kicad is now able to detect errors that could not be detected earlier. I’m aware of how STM32 cube works, and I remember having asked for this feature, maybe a couple of years ago. Anyway, to summarize, it’s perfect, and the only possible improvement would add a text when no alternate name is selected, as mentioned above. Like “select alternate name”. And while we are at it, it’s not realy a matter of name, but also functionality, so “select alt pin function” could be even better.

Back after some time. I’m trying to use what I did earlier, and in fact I’m not sure that this new functionality is an advantage. The problem is that now I have a symbol with a single label (I mean the functionality, like P6.5). This means that if I want to use for instance the A5 functionality (analog 5. which is on the same pin as P6.5), then I have to know where it is. This one is simple, Port6 is analog for all the MSP430s. So P6.x van also be remap tp A6. Now what should I do if I don’ t know for instance the location of UART2? Opening a pdf is certainly a solution, but It would be good if I could search from the schematic editor. For instance, right click on the component, have a “find” menu in which I would key in “UART2”

Is there an existing method? The alternate pin panel is apparently not searchable. At least not with the standard cmd-F.

Thanks for your reply. Yes, that’s what I ended up doing. I have also added a NC option for all the pins so that the schematic better retlects what I do.

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