blocking assignments in systemverilog

Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

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Procedural Assignments

Blocking assignments, race around condition: a problem with blocking assignment.

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Blocking and Non-blocking Assignment in Verilog

• Assignment is only done in procedural block(always ot initial block)
• Both combintational and sequential circuit can be described.
• Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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Comments (1)

hey in blocking assignment do we get shift in data i dont think so . we get all values same and equal to d.

Please do not focus on the module name; focus on how the netlist is generated after the synthesis.

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Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following:

We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is asserted (synchronous reset), then we go on with normal logic. If we look closely we see that in the case of combinational logic we had "=" for assignment, and for the sequential block we had the "<=" operator. Well, "=" is blocking assignment and "<=" is nonblocking assignment. "=" executes code sequentially inside a begin / end, whereas nonblocking "<=" executes in parallel.

I was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel. After all, you can make blocking assignments with assign statements outside of always blocks, and those all run in parallel. Is this a mistake, or is the behavior different inside an always block? And, if the behavior IS different inside an always block, can nonblocking assignments be made outside an always block?

3 Answers 3

was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel.

Blocking assignment executes "in series" because a blocking assignment blocks execution of the next statement until it completes. Therefore the results of the next statement may depend on the first one being completed.

Non-blocking assignment executes in parallel because it describes assignments that all occur at the same time. The result of a statement on the 2nd line will not depend on the results of the statement on the 1st line. Instead, the 2nd line will execute as if the 1st line had not happened yet.

• \$\begingroup\$ So what about assign statements? Are they just in a whole class of their own? \$\endgroup\$ –  Void Star Commented Nov 24, 2013 at 4:25
• 6 \$\begingroup\$ Yes, assign statements occur outside of always blocks and are generally used to describe to combinatorial (un-latched) logic (while always blocks, with some exceptions, describe sequential logic). AFAIK, assign statements always execute "in parallel" whenever their LHS has a value change. \$\endgroup\$ –  The Photon Commented Nov 24, 2013 at 4:28
• \$\begingroup\$ Okay... I'm starting to get the impression that Verilog just isn't the most elegantly designed language. This is gonna be like learning C was. \$\endgroup\$ –  Void Star Commented Nov 24, 2013 at 5:30
• 2 \$\begingroup\$ Verilog was designed to "describe" hardware that already exists. Using it as a language to design (synthesize) hardware is a hack. \$\endgroup\$ –  The Photon Commented Nov 24, 2013 at 6:02
• 6 \$\begingroup\$ if Verilog "like learning C" is a problem, take a look at VHDL. Some people have fairly strong preferences for one or the other. To some, VHDL is just too verbose. To me, it's much better thought out. (signal/variable assignment semantics are much clearer than blocking/non for example). stackoverflow.com/questions/13954193/… and sigasi.com/content/vhdls-crown-jewel You may prefer it or hate it. But it's worth a look. \$\endgroup\$ –  user16324 Commented Nov 24, 2013 at 10:20

Assign statements are neither "blocking" or "nonblocking", they are "continuous". The output of an assign statement is always equal to the specified function of it's inputs. "blocking" and "nonblocking" assignments only exist within always blocks.

A blocking assignment takes affect immediately it is processed. A nonblocking assignment takes place at the end of processing the current "time delta".

always blocks can be used to model either combinatorial or sequential logic (systemverilog has always_comb and always_ff to make this explicit). When modeling combinatorial logic it's usually more efficient to use = but it typically doesn't really matter.

When modelling sequential logic (e.g. always @(posedge clk) ) you normally use nonblocking assingments. This allows you to deterime the "state after the clock edge" in terms of "the state before the clock edge".

It is sometimes useful to use blocking assignments in sequential always blocks as "variables". If you do this then there are two key rules to bear in mind.

• Do not access a reg that is set with blocking assignments inside a sequential always block from outside the always block it is assigned in.
• Do not mix blocking and nonblocking assignments to the same reg.

Breaking these rules is likely to result in synthesis failures and/or behaviour differences between simulation and synthesis.

• \$\begingroup\$ ""Do not access a reg that is set with blocking assignments inside a sequential always block from outside the always block it is assigned in."" Can you please explain it? \$\endgroup\$ –  user125575 Commented Oct 4, 2016 at 6:44
• 2 \$\begingroup\$ Different sequential always blocks do not have a defined order. So reading a "reg" set with a blocking assingment in one always block from another always block will lead to unpredicable behaviour. \$\endgroup\$ –  Peter Green Commented Oct 4, 2016 at 15:23
• \$\begingroup\$ And even if it appears to work in simulation, a synthesis tool should look at that and say "nope". I use local regs for those intermediate vars, and make sure that they are always assigned to on every clock before being read, so that no 'storage' is implied. \$\endgroup\$ –  greggo Commented Mar 30, 2017 at 11:57
• \$\begingroup\$ IIRC at least in quartus it is only considered a warning not an error. \$\endgroup\$ –  Peter Green Commented Mar 30, 2017 at 11:59
• \$\begingroup\$ You should not be using nonblocking assignment in combinational logic, it can lock up the simulation. For more details, refer this answer: electronics.stackexchange.com/a/506047/238188 \$\endgroup\$ –  Shashank V M Commented Oct 5, 2020 at 14:55

The term Blocking assignment confuses people because the word blocking would seem to suggest time-sequential logic. But in synthesized logic it does not mean this , because everything operates in parallel .

Perhaps a less confusing term would be immediate assignment , which would still differentiate the intermediate results of combinational logic from the inputs to non-transparent memory elements (for example clocked registers), which can have delayed assignment .

From a legalistic standpoint, it all works out very nicely. You can, in fact, consider the = to be a blocking (time-sequential) operation even within always_comb sequences. However, the distinction between time-sequential and parallel makes absolutely no difference in this case because the always_comb block is defined to repeat until the instruction sequence converges on a stable state -- which is exactly what the hardware circuitry will do (if it meets the timing requirements).

The synthesizable subset of Verilog (and especially SystemVerilog) is extremely simple and easy to use -- once you know the necessary idioms. You just have to get past the clever use of terminology associated with the so-called behavioral elements in the language.

• \$\begingroup\$ In behavioral coding styles ( as compared to RTL ), the distinction between blocking and non-blocking can be relevant. In some cases, the synthesis tool may be able to infer functionally equivalent RTL from behavioral component designs. \$\endgroup\$ –  Brent Bradburn Commented Jul 21, 2015 at 17:28
• \$\begingroup\$ Of course the procedural mode of SystemVerilog, applicable especially to initial statements within program blocks, uses (time-sequential) blocking assignment exclusively. This is useful for testbench design, but generally not for RTL specification. \$\endgroup\$ –  Brent Bradburn Commented Dec 18, 2015 at 18:58

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Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

• Blocking Assignments
• Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

• Blocking assignments (=) are done sequentially in the order the statements are written.
• A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Non-Blocking assignments

• Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
• The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
• The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
• Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

For Synthesis (Points to Remember):

• One must not mix “<=” or “=” in the same procedure.
• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
• “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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Related posts:

• Synthesis and Functioning of Blocking and Non-Blocking Assignments.
• Delay in Assignment (#) in Verilog
• Ports in Verilog Module
• Module Instantiation in Verilog

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Verilog Blocking & Non-Blocking assignments elaborated

• Post author By Kevin
• Post date 20 October 2020

Blocking / Non-Blocking assignment rules

The main reason to use either Blocking or Non-Blocking assignments is to generate either combinational or sequential logic.

In non-blocking assignments (<=), all registers inside the always block are updated at the end. In blocking assignments (=), the registers are updated immediately.

Whether or not a flip-flop is inferred from a blocking assignment depends on whether or not the value of the variable being assigned needs to be remembered from one clock edge to the next.

It is good practice to separate combinational and sequential code as much as possible. In verilog, if we want to create sequential logic can use a clocked always block with non-blocking assignments. If on the other hand we want to create combinational logic can use an always block with blocking assignments. Best not to mix the two in the same always block but if they are mixed, need to be careful when doing this. Its up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a flip-flop or not. If the signal is read before being assigned (eg fig2 below), the tools will infer sequential logic.

For simplicity purposes only showing in the verilog examples below the Always Block. These Always blocks are blocks of sequential logic since it involves a clock.

If on an active clock edge, the variable tmp is being assigned a value before it’s value is used (ie ‘write before read’ case) then no flip-flop is required & synthesis will not infer it as shown in fig1 below.

If the value of the reg is used before a new value is assigned to it (ie ‘read before write’ case), then the value that is used will be the value that was assigned on a previous clock. Therefore a flip-flop is required here as shown in fig2 below.

If all non-blocking assignments are used within the always block, it will look like :

Non-blocking assignments always imply flip-flops (order of assignments doesn’t matter). Same block diagram is inferred on both cases as shown in fig3 above. They result in simultaneous or parallel statement execution.

Programming Variables in SystemVerilog: Blocking vs. Non-Blocking Assignments

Abstract: Learn the difference between blocking and non-blocking assignments in SystemVerilog and when to use each one.

SystemVerilog is a hardware description and hardware verification language used to model, design, and verify electronic systems. One of the key concepts in SystemVerilog is the use of variables and assignments. This article will focus on the two types of assignments in SystemVerilog: blocking and non-blocking assignments.

Blocking Assignments

In SystemVerilog, blocking assignments are used to assign values to program variables. A program variable is a variable that is declared using the reg or integer data type. Blocking assignments are denoted by the = symbol and are executed in order, from left to right.

In the above example, the value of variable a is assigned to variable b , and then the value of variable b is assigned to variable c . This type of assignment is called a blocking assignment because the assignment of the right-hand side expression to the left-hand side variable blocks the execution of any further statements until the assignment is complete.

Non-Blocking Assignments

Non-blocking assignments are used to assign values to non-program variables. A non-program variable is a variable that is declared using the logic , bit , or wire data type. Non-blocking assignments are denoted by the <= symbol and are executed simultaneously, not in order.

In the above example, the value of variable a is assigned to variable b , and the value of variable b is assigned to variable c , all at the same time. This type of assignment is called a non-blocking assignment because the assignment of the right-hand side expression to the left-hand side variable does not block the execution of any further statements.

Key Concepts

It is important to understand the key concepts of blocking and non-blocking assignments in SystemVerilog. Blocking assignments are used to assign values to program variables and are executed in order, from left to right. Non-blocking assignments are used to assign values to non-program variables and are executed simultaneously, not in order.

In general, it is recommended to use non-blocking assignments when assigning values to non-program variables, as this will ensure that the values are assigned at the same time and will not cause any race conditions. Blocking assignments should be used when assigning values to program variables, as this will ensure that the assignments are executed in order.

• SystemVerilog uses blocking and non-blocking assignments to assign values to variables.
• Blocking assignments are used to assign values to program variables and are executed in order.
• Non-blocking assignments are used to assign values to non-program variables and are executed simultaneously.
• It is recommended to use non-blocking assignments when assigning values to non-program variables and blocking assignments when assigning values to program variables.
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Verification Guide

SystemVerilog NonBlocking assignment

Nonblocking assignment.

• non-blocking assignment statements execute in parallel
• In the non-blocking assignment, all the assignments will occur at the same time. (during the end of simulation timestamp)

Nonblocking assignment example

In the below example, a and b are initialized with values 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment values expected in a and b are 15 and 20 respectively. but these values will get assigned only after the simulation time-stamp.

Simulator Output:

Nonblocking assignment example-2

In the below example, a and b are initialized with value 10 and 15 respectively. x<=a+b and y<=a+b+x value of x is sum of a (10) and b (15). -> x=10+15=25. value of y is sum of a (10) ,b(15) and x (0) -> became at current simulation time-stamp value of x=0. new value will get assigned at the end of current time stamp, and new value will be available only after the current time-stamp). therefore y=10+15+0=25;

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Mixing nonblocking and blocking assignments in an always_ff block of an arbiter

I'm unable to wrap my head around Example 10-3 in SystemVerilog For Design book by Stuart Sutherland (and co.).

See line 232 of :

https://code.google.com/p/vak-opensource/source/browse/trunk/hardware/systemverilog/utopia-example/squat.sv?r=185

Here is the snippet of code. My question will follow.

Specifically, my question is about the blocking assignment for breakVar and RoundRobin . I read somewhere that the variables are locally evaluated, but I can't picture in terms of gates how the logic is synthesized. Does RoundRobin get synthesized to a state register?

Most guidelines state to never mix blocking and nonblocking assignments. Is there a better way to represent something like this? Is it okay now in SystemVerilog designs to mix both types of assignments given that it is in an always_ff block?

• system-verilog
• round-robin

2 Answers 2

You should never mix blocking and nonblocking assignments to the same variable. breakVar is a temporary variable that will be synthesized into combinatorial logic because it is always written to first, then read. There is no state to be saved. RoundRobin is a local variable that is being used as both an intermediate and state variable. But because it is only accessed from within the always_ff block, there is no danger of a race condition.

A temporary variable is just a symbolic way to represent a piece of an equation. Here is a different but simpler example:

This is equivalent to writing the following (but might be harder to understand)

In the two examples above, counter will always be synthesized as a register because it is read before written. It won't matter if we used a blocking or nonblocking assignment because we never read counter after writing it. There is no race condition within this always_ff block using blocking assignment but there could be if there was another always_ff block trying to read it. Since full and brimming are written before being read, they do not have to be registered.

To summarize, a variable get synthesized as a register if any of these conditions are true

• A variable is read before being written within the same always block. Note that even if a non-blocking assignment statement appears first, the read happens first because the write get scheduled to happen later.
• Due to conditional or looping statements, a variable is sometimes read without being written
• A variable is written in an always_ff block and read outside the block.

• I'm not sure that's correct - RoundRobin in this case is a register, should really be using non-blocking assignment. –  Chiggs Commented Jun 13, 2014 at 14:34
• I was half-correct - RoundRobin stores state but is also read after being written in the loop and so requires a blocking assignment... My comment was slightly misleading, but you spotted the deliberate mistake ;) –  Chiggs Commented Jun 13, 2014 at 15:32
• 1 The 2 always block approach is cleaner, though it requires a little more typing. One always_comb for all blocking assignments including next_state values, and an always_ff for non-blocking assigning the states to their next_state. This allows see the D pin in wave from which is useful for debug. I find it makes ECOs easier to do and documented. According to Cliff's SNUG2003 paper on FSM , the 2-always approach gives better area and timing but I think it is really tool/version dependent. –  Greg Commented Jun 13, 2014 at 17:24
• @dave_59, could you please elaborate a little on how a temporary variable is synthesized? –  user12311164 Commented Oct 14, 2020 at 7:47
• 1 Updated answer. –  dave_59 Commented Oct 17, 2020 at 22:18

Totally agreed with @jonathan answer.

You should always split your logic elements in always_comb block and sequential elements in always_ff block.

If you write a code that is so closely stitched together ( both combi and sequential elements in same block) even though it is correct and compliant with system verilog spec, some older versions of simulator or newer simulators being developed may infer it in wrong way.

Your code will not be clean and comprehensible to others.

Also by writing in above style you are just compacting the lines of code, even though the logic remains same. There is no sense in writing a compact code if it hampers the readability of the code.

Now as far as blocking and non-blocking statements usage is concerned, I think that debate is closed now. It is now more a rule than a guideline to use blocking statements in always_comb block and non-blocking in always_ff block.

However the answer to all your questions are explained in this superb paper by Clifford E Cummings Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

And if you are new to verilog/system verilog design I suggest you read all their papers, They are very useful and sets up a good base for a RTL Design Engineer.

Also it may be too much to tell here but if you are looking how to segregate your code in combi and sequential block you can have a look at code generated by bluespec

The signal names are difficult to comprehend in one go, but if you look closely the code is very neat logically and does not leave anything on the whims of simulation and synthesis tools.

• The paper you have quoted is about Verilog not SystemVerilog. –  user12311164 Commented Oct 17, 2020 at 6:23
• @ShashankVM SystemVerilog is a superset of Verilog, same concepts apply. –  nincompoop_ Commented Oct 17, 2020 at 8:43
• compliant with system verilog spec, some older versions of simulator or newer simulators being developed may infer it in wrong way then that's a bug and order the vendor to fix it ASAP, they must follow the specs or they call it something else. That's also a sufficient legal fault to invalidate any purchase of such a simulator. (done it and we won) –  None Commented Apr 1, 2022 at 3:23

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