assignment types vhdl

VHDL Record, Array and Custom Types

In this post, we talk about the methods we can use to create our own custom data types in VHDL , including arrays and record types.

In the previous post we talked about the basic predefined types in VHDL . Whilst these are adequate for the majority of cases there are occasions when we require a custom data type in our code.

In VHDL, the most commonly used custom types are the enumerated types. These provide us with a technique for creating an entirely new type with custom values.

However, we can also create sub types which allow us to modify the range of values in one of the predefined VHDL types. In fact, the inbuilt VHDL positive and natural types are both example of subtypes which limit the range of values the integer can accept.

In addition to this, we can also use array and record types in our VHDL designs. This can provide us with a more structured design which is easier to maintain.

In the rest of this post we will at the methods we use to create all of these custom types in our VHDL code.

Creating Custom Types

When we write VHDL code, there are instances when the predefined types we wish to create a new type. One of the most common use cases is creating an enumerated type which we us to implement finite state machines (FSM) .

Actually there are two ways in which we can create a custom type in VHDL. We can either create an entirely new type or we can create a subtype .

Let's take a look at both of these methods.

• Type Declaration in VHDL

It is possible for us to create an entirely new type to use in our VHDL design. To do this, we must create a new name for our type and then associate some valid values with it.

The code snippet below shows the general syntax we use to create an new type.

The list of values is a comma separated list of all the values of our type can have.

When declaring a new type in VHDL we typically create an enumerated type. This means our list of values are just strings, or words, which we can assign to any instances of the type.

As an example, let's create a new type which we use to store the state of a small FSM. This is one of the most common reasons for creating a new type in VHDL.

For this example, our FSM will have just four states - idle, starting, runnning and stopping.

The code snippet below shows how we would create this type in VHDL. We can see that this is an enumerated type, meaning the list of values are simple strings.

Once we have created this type, we can create an instance of it in our code. We can then assign any value to it which we have listed in the declaration.

The code snippet below shows how we would create a signal using our custom type and assign it to the idle state.

• Subtype in VHDL

The second method we can use to create a custom type modifies one of the existing types. To do this, we use the subtype VHDL keyword and restrict the range of valid values which the new type can take.

The code snippet below shows the general syntax we use when creating a sub type.

One of the most common uses for the sub type keyword in VHDL is to restrict the number of bits in an integer type.

As an example, we may want to declare an integer which only uses 8 bits. In this case we can declare a new subtype and limit the maximum value to 255. The code snippet below shows how we would do this.

After we have created a new subtype, we can create instances of it to use in our VHDL design. We can then assign it any of the values we specified in the declaration.

The code snippet below shows how we would create a signal using our new type.

• Creating Array Types in VHDL

We can create our own array types in VHDL. To do this, we include the array keyword in the type definition. We must also declare the number of elements in the array.

The code snippet below shows the general syntax we use to declare an array type in VHDL.

The <type> field in the above construct can accept any VHDL type, including custom types we have declared. This means we can also build multidimensional arrays by using array types in this field.

The <range> field in the above example can be built using the downto and to VHDL keywords which we have seen before.

However, we can also use two special constructs which effectively create an unconstrained array type. This allows us to define the size of the array whenever we declare a port or signal which uses it.

To do this, we use the natural <range > or positive <range> keywords in the <range> field. The difference between the two is that the natural <range> option allows for zero based array numbering whereas positive <range> doesn't.

The VHDL code below shows the general syntax we use to create unconstrained array types.

Once we have declared a custom array type it can be used in an entity port, as a signal or a as a variable.

• An Example Array Type

To demonstrate how we declare a custom array type, lets consider a basic example. For this example we will create an array of 8 bit std_logic_vector types.

In addition, we will not constrain the array when we declare it. Instead, we will use the natural <range> construct so that we can change the size as we declare signals.

The code snippet below shows how we declare and use our custom array type.

Record Type in VHDL

We can create more complex data types in VHDL using a record. Records can contain any number of different signals which we want to group together. These signals don't need to be of the same type.

We can think of records as being roughly equivalent to structs in C.

We often use records to simplify the port list in a VHDL entity . If we have a number of common signals, we can group them together in a record. We can then use this record as part of the entity which reduces the number of ports we require.

Using record types in an entity can also improve the maintainability of our code. The main reason for this is that we only need to manage the contents of a record in the place it is declared. Therefore, we can change connections in our ports just by modifying the record type. If our design features multiple modules which use the same record, this can reduce the effort require to modify connections between entities.

• Declaring and Using a Record in VHDL

When we want to use a record in VHDL we must declare it as a type. We most commonly declare records inside a VHDL package . This allows us to use the record type in multiple different design files.

The code snippet below shows the general syntax we use to declare a record type in VHDL.

After we have declared a record type, we can use it in the exact same manner as any other port or signal in our VHDL design. We can assign data to individual elements in the record or to the entire array.

The code snippet below shows the two methods we can use to assign data to the record.

It is also possible for us to include records as elements in an array.

• An Example Record Type

Lets consider a basic example to better demonstrate how a record type works in VHDL. For this example, we will write a record which contains all the signals required in a UART interface.

The UART interface consists of 4 different signals. Each of these signals are a single bit which means we can use a std_logic type to model them.

The code snippet below shows how we would declare this record type.

After we have created the record, we can then use it in the type field for any port or signal in our VHDL design.

The code snippet below shows hows we would declare a signal which uses our UART record type.

Finally, we will obviously also want to drive data onto our record signal. The VHDL code snippet below gives some examples of how we can assign data to the record.

Write some VHDL code which creates an enumerated type for an FSM. The FSM has 4 states – idle, running, stopped and error

Create an integer subtype which can have a value between 5 and 200.

Write some VHDL code which declares an array of 8 32-bit std_logic_vectors

Write a record type which consists of an 8 bit unsigned type, a std_logic type and an unconstrained integer.

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Data Types in VHDL

In this article, we shall discuss data types in VHDL. After reading this article, you’ll be able to answer the following questions.

What are data types?

In VHDL, we define datatypes while initializing signals, variables, constants, and generics.

Also, VHDL allows users to define their own data types according to their needs, and those are called user-defined data types.

User-defined data types can be defined in a separate file and shared as a library. You can define a bunch of custom data types and put them in a library and use that whenever you want. Sort of like your personal toolkit!

Due to its usefulness, it is the most popular and widely used library in VHDL. It has useful datatypes like std_logic and std_ulogic which helps us to make simulation much more practical. And to make our VHDL programming easy, we use IEEE’s library and its functions quite often.

Significance of datatypes

Similarly, we store data values in variables of a suitable type. And the same analogy continues for other data objects like signals, constants, etc.

Consider a ‘signal Q’ whose datatype we don’t know yet. It is initialized with a value ‘0’. If we wish to change its value to ‘1’ later on. How we’ll do it?

As a programmer, you have the freedom to use a data type, but you should also utilize your wisdom to choose a suitable one.

Data types in the standard library

There are many data types defined in the standard library of VHDL. To make them easy to understand, we categorize them into the following four types:

Enumerated type

Boolean data type.

A Boolean type data object can have a single value. Either ‘FALSE’ or ‘TRUE.’ That’s it. The logical operations that can be performed on Boolean variables are “and, or, not, nand, nor, xor.”

Bit data type

A Bit type of data object can either have ‘0’ or ‘1’. The logical operations that can be performed on Bit variables are the same as of Boolean, i.e. “and, or, not, nand, nor, xor.”

Initializing a Bit type variable and a signal with an initial value:

Character data type

A character type data object can hold any one character or special character at a time or can hold sum defined literal like NUL, SOX, STX, etc.

All possible enumeration for a character data type

Severity levels.

The severity level data type can have the values ‘NOTE’, ‘WARNING,’ ‘ERROR,’ ‘FAILURE.’ Severity levels are used in assertion statements, which will be discussed in detail in an upcoming article, but, in short, they behave as logs (think of them like personal paper flags) while simulation to indicate if any error occurs and what is its severity.

So default value for data objects of datatype bit is ‘0’. And the same goes for all data types as mentioned in the table below

Numeric type

Integer data type.

Now, what are subtypes you ask, in short, a subtype is a datatype which has constrained values of its base type. Sound confusing?

Real data type

It can hold floating-point numbers ranging from -1.0E38 to +1.0E38. These are very helpful for precise calculation. For example, if we need to use the value of pi (π) for some calculations, then we can’t use an integer to store its value (3.14159). An integer can only store 3, which decreases preciseness of calculations. But a real can store floating digits of up to 6 decimal places.

Array data types

Bit vector -A bit_vector is simply an array of grouped bits, they are useful while defining multiple pin inputs. Consider an example. You are creating a 4-bit adder so you’ll need 4-bit inputs, rather than defining them individually you can use:

Miscellaneous

There are two data types in the standard library, i.e., ‘TIME.’ This is used to store values that can be further utilized for timing operation, like creating specific delays. Some units of time are also defined in the standard library, as shown below:

Data types from non-standard libraries

We use it to represent much more practical details of digital signals in circuits and wires.

'H' : This signal is also weak but it should probably go to 1

std_logic – This datatype has the same enumeration as of std_ulogic . However, the difference is that std_logic is resolved and we don’t need extra resolution function.

'L' : This signal is also weak that it should probably go to 0

Initializing a Std_logic type variable and a signal with an initial value:

The statement above assigns ‘0’ to input(0), ‘1’ to input(1), and so on.

In the code above, we have created a record named ‘MODULE,’ and it has 4 data objects inside it. Now MODULE is a datatype in itself.

The above line of code assigns “50” to SIZE, “20 ns” to DELAY, “3” to NO_OF_INPUTS, and “2” to NO_OF_OUTPUTS.

Bit and bit_vector

In the above code, three ports are initialized, two inputs, and one output. For data input in 2×1 mux, we need 2-bit input we may use two different bits as

This creates 2-bit input as input(0) and input(1) and assigning values to them is way more comfortable as

As always, if you have any queries, we would love to address them. Just drop in a comment in the comments section below.

Related courses to Data Types in VHDL

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Cmos - ic design course.

A free course as part of our VLSI track that teaches everything CMOS. Right from the physics of CMOS to designing of logic circuits using the CMOS inverter.

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Most logic synthesis tools accept one-dimensional arrays of other supported types. 1-D arrays of 1-D arrays are often supported. Some tols also allow true 2-D arrays, but not more dimensions.

Note that arrays are usually implemented using gates and flip-flops, not ROM's and RAM's.

Array types have not changed in VHDL -93.

Assignment Symbol in VHDL

VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols:

Either of these assignment statements can be said out loud as the word “gets”. So for example in the assignment: test <= input_1; You could say out loud, “The signal test gets (assigned the value from) input_1.”

Note that there is an additional symbol used for component instantiations (=>) this is separate from an assignment.

Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator , otherwise it’s an assignment.

One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is good practice to assign all signals in an FPGA to a known-value when the FPGA is initialized. You should avoid using a reset signal to initialize your FPGA , instead use the := signal assignment.

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courses:system_design:vhdl_language_and_syntax:extended_data_types:arrays

More Arrays

• Constrained or unconstrained size
• Range specification necessary
• The index set can be of any type

Arrays are a collection of a number of values of a single data type and are represented as a new data type in VHDL.

It is possible to leave the range of array indices open at the time of definition. These so called unconstrained arrays can not be used as signals, however, i.e. the index range has to be specified in the signal declaration then. The advantage of unconstrained arrays is the possibility to concatenate objects of different lengths, for example, because they are still of the same data type.

This would not be allowed if each array length was declared as separate data type. VHDL does not put any restrictions on the index set of arrays, as long it is a discrete range of values. It is even legal to use enumeration types, as shown in the code example, although this version is not generally synthesizable.

Multidimensional Array

• Array of array
• Multidimensional array
• Different referencing
• Barely supported by synthesis tools

Multidimensional arrays can simply be obtained by defining a new data type as array of another array data type (1). When accessing its array elements, the selections are processed from left to right, i.e. the leftmost pair of brackets selects the index range for the “outermost” array. Thus ’MATRIX_3x8(2)’ selects the second ’INTEGER_VECTOR’ of ’MATRIX_A’.

The range enclosed in the next pair applies to the array that is returned by the previous slice selection, i.e. ’MATRIX_3x8(2)(4)’ returns the fourth integer value of this ’INTEGER_VECTOR’. Multiple dimensions can also be specified directly within a new array definition (2). The ranges of the different dimensions are separated by ’,’ symbols. If a whole row or column is to be selected, the range has to be provided in the slice selection. Multidimensional arrays are generally synthesizable up to dimension 2, only.

Aggregates and Multidimensional Arrays

• Aggregates may be nested
• Aggregates can be used to make assignments to all elements of a multidimensional array

The most convenient way to assign values to multiple array elements is via the aggregate mechanism. Aggregates can also be nested for this purpose. With an aggregate one can assign to all elements of an array a specific value in a clear fashion.

Chapters of System Design > VHDL Language and Syntax > Extended Data Types

• Introduction
• Standard Logic Type
• Enumeration Types

Chapters of System Design > VHDL Language and Syntax

• General Issues
• VHDL Structural Elements
• Process Execution
• Extended Data Types
• Sequential Statements
• Subprograms
• Subprogram Declaration and Overloading
• Concurrent Statements

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VHDL: How does one assign custom values to identifiers of an enumerated type?

For a design with seven segment displays, it will be easier in modelsim simulation if one can see the actual display value going into the seven segment display e.g hexadecimal D which is "1000010" in binary could appear as an enumerated type 'ss_D' in the simulation waveform. How does one create an enum with custom assigned values for this purpose?

I know it does not hurt to just concentrate on the value going into the decoder for the seven segment display instead and see it as hexadecimal in the wave window. But the question here is, generally how to assign custom value to VHDL enum type?

• 7segmentdisplay

• 1 \$\begingroup\$ Is your goal to visualize the LED signals in ModelSim or to represent them symbolically as enumerated type in VHDL? If it's only the former then you could define a custom radix in ModelSim, like so: radix define led-state { B"1000010" "ss_D" } \$\endgroup\$ –  Tony K Commented Dec 20, 2015 at 2:25
• \$\begingroup\$ @TonyK This works fine, but is not fully supported in ModelSim light versions like ModelSim Altera Edition. \$\endgroup\$ –  Paebbels Commented Dec 20, 2015 at 10:38

2 Answers 2

See Ashenden "Designer's Guide to VHDL" (chapter 20.2).

given the type definition from the other answer

we can assign a representation to it via an attribute:

and then we should be able to access that value via the attribute syntax:

I do not know how Modelsim will display the LED_port signal, but I would expect it to display the ss_enum signal using its enumeration values ss_D etc.

In practice I find it unnecessary to assign encodings, I would declare a constant array for this purpose, the syntax is shorter and tidier, and it'll usually synthesise down to the same thing.

This approach doesn't answer your waveform display question, but I find it's better to make the simulation self-checking; then, looking at waveforms is the exception (when something went wrong) rather than the rule, and therefore it's much less important.

Enumerated types are easy to declare:

This is not a character enumeration type (all of it's members are identifiers).

Essentially you can association a value with an identifier or character literal. In this case the hex value input to the loop up used to produce your seven segment display value is also used to set the value of a signal of the enumerated type:

You can think of it as extra information unless you use the enumerated type as the index type to your seven segment value look up. (And VHDL allows you to do that).

If as Dave Tweed suggests you wanted to recognize seven segment values in a sparse fashion, you'd map them to your enumerated type:

In this case that sparse look up is done with a function using a case statement (and we can see the example is sparse indeed).

You can see there's an added enumeration value for seven segment values that aren't useful mapped.

That gives us:

This method can also be done in most waveform viewers in some generally non-portable fashion. Because in this case the enumerated type signal wouldn't be used anywhere you'd expect it to get gate eaten in synthesis. (Without any output ports mapped to pins this entire example 'design' would be gate eaten anyway).

• \$\begingroup\$ I think you may have missed the point of the question. The way I read it, the OP wants to take an arbitrary 7-bit value on a bus, say, "1000010", and have it displayed as "ss_D" in the simulator. Or in the more general sense, can one assign specific bit patterns to specific enumeration symbols without enumerating all 2^N possibilities? \$\endgroup\$ –  Dave Tweed Commented Dec 20, 2015 at 2:28
• \$\begingroup\$ "But the question here is, generally how to assign custom value to VHDL enum type?" Don't conflate position and value. You can supply the enumerated types as input to what ever produces your seven segment values "(And VHDL allows you to do that)." \$\endgroup\$ –  user8352 Commented Dec 20, 2015 at 2:43
• \$\begingroup\$ @user1155120 you are correct in your understanding of the question. \$\endgroup\$ –  quantum231 Commented Dec 20, 2015 at 15:31

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VHDL assigning literals

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

• unsigned-integer

3 Answers 3

See other answers, and note that for non-zero literals, you probably want to do something like:

Substitute a literal for n . This works for n =0 too, of course, but it's not as tidy as (others => '0') .

• LCD_DATA'LENGTH isn't available until after the semicolon. IEEE Std 1076-1993 10.3 Notes "2—The rules defining immediate scope, hiding, and visibility imply that a reference to an identifier, character literal, or operator symbol within its own declaration is illegal (except for design units). The identifier, character literal, or operator symbol hides outer homographs within its immediate scope—that is, from the start of the declaration. On the other hand, the identifier, character literal, or operator symbol is visible only after the end of the declaration (again, except for design units)." –  user1155120 Commented Mar 18, 2014 at 23:02
• For -2008 that's Section 12.3 Visibility, same Note 2. –  user1155120 Commented Mar 18, 2014 at 23:16
• The original erroneous answer provided variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, LCD_DATA'length); Essentially something isn't available until it is declared and the declaration is variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ; , which is where the after the semicolon comment comes from. See IEEE Std 1076-1993 4.3.1.3 (6.4.2.4 -2008) Variable declarations. –  user1155120 Commented Mar 18, 2014 at 23:26
• Yeah, I'm so used to using that construct in processes, etc., I forgot it was illegal in declarations. –  fru1tbat Commented Mar 19, 2014 at 13:53

And for the 2nd part of your question while adding number of this type.

Check whether you have used above libraries in the code or not.

unsigned is related to std_ulogic, where the value for an element would be '0'.

which provides an aggregate for the default assignment with all elements set to '0'.

You can't assign a single element of integer type to an array of std_ulogic elements.

You can add signed or unsigned to a natural (unsigned) or integer (signed) using "+" functions defined in package numeric_std:

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