assignment types vhdl

VHDL Record, Array and Custom Types

In this post, we talk about the methods we can use to create our own custom data types in VHDL , including arrays and record types.

In the previous post we talked about the basic predefined types in VHDL . Whilst these are adequate for the majority of cases there are occasions when we require a custom data type in our code.

In VHDL, the most commonly used custom types are the enumerated types. These provide us with a technique for creating an entirely new type with custom values.

However, we can also create sub types which allow us to modify the range of values in one of the predefined VHDL types. In fact, the inbuilt VHDL positive and natural types are both example of subtypes which limit the range of values the integer can accept.

In addition to this, we can also use array and record types in our VHDL designs. This can provide us with a more structured design which is easier to maintain.

In the rest of this post we will at the methods we use to create all of these custom types in our VHDL code.

Creating Custom Types

When we write VHDL code, there are instances when the predefined types we wish to create a new type. One of the most common use cases is creating an enumerated type which we us to implement finite state machines (FSM) .

Actually there are two ways in which we can create a custom type in VHDL. We can either create an entirely new type or we can create a subtype .

Let's take a look at both of these methods.

• Type Declaration in VHDL

It is possible for us to create an entirely new type to use in our VHDL design. To do this, we must create a new name for our type and then associate some valid values with it.

The code snippet below shows the general syntax we use to create an new type.

The list of values is a comma separated list of all the values of our type can have.

When declaring a new type in VHDL we typically create an enumerated type. This means our list of values are just strings, or words, which we can assign to any instances of the type.

As an example, let's create a new type which we use to store the state of a small FSM. This is one of the most common reasons for creating a new type in VHDL.

For this example, our FSM will have just four states - idle, starting, runnning and stopping.

The code snippet below shows how we would create this type in VHDL. We can see that this is an enumerated type, meaning the list of values are simple strings.

Once we have created this type, we can create an instance of it in our code. We can then assign any value to it which we have listed in the declaration.

The code snippet below shows how we would create a signal using our custom type and assign it to the idle state.

• Subtype in VHDL

The second method we can use to create a custom type modifies one of the existing types. To do this, we use the subtype VHDL keyword and restrict the range of valid values which the new type can take.

The code snippet below shows the general syntax we use when creating a sub type.

One of the most common uses for the sub type keyword in VHDL is to restrict the number of bits in an integer type.

As an example, we may want to declare an integer which only uses 8 bits. In this case we can declare a new subtype and limit the maximum value to 255. The code snippet below shows how we would do this.

After we have created a new subtype, we can create instances of it to use in our VHDL design. We can then assign it any of the values we specified in the declaration.

The code snippet below shows how we would create a signal using our new type.

• Creating Array Types in VHDL

We can create our own array types in VHDL. To do this, we include the array keyword in the type definition. We must also declare the number of elements in the array.

The code snippet below shows the general syntax we use to declare an array type in VHDL.

The <type> field in the above construct can accept any VHDL type, including custom types we have declared. This means we can also build multidimensional arrays by using array types in this field.

The <range> field in the above example can be built using the downto and to VHDL keywords which we have seen before.

However, we can also use two special constructs which effectively create an unconstrained array type. This allows us to define the size of the array whenever we declare a port or signal which uses it.

To do this, we use the natural <range > or positive <range> keywords in the <range> field. The difference between the two is that the natural <range> option allows for zero based array numbering whereas positive <range> doesn't.

The VHDL code below shows the general syntax we use to create unconstrained array types.

Once we have declared a custom array type it can be used in an entity port, as a signal or a as a variable.

• An Example Array Type

To demonstrate how we declare a custom array type, lets consider a basic example. For this example we will create an array of 8 bit std_logic_vector types.

In addition, we will not constrain the array when we declare it. Instead, we will use the natural <range> construct so that we can change the size as we declare signals.

The code snippet below shows how we declare and use our custom array type.

Record Type in VHDL

We can create more complex data types in VHDL using a record. Records can contain any number of different signals which we want to group together. These signals don't need to be of the same type.

We can think of records as being roughly equivalent to structs in C.

We often use records to simplify the port list in a VHDL entity . If we have a number of common signals, we can group them together in a record. We can then use this record as part of the entity which reduces the number of ports we require.

Using record types in an entity can also improve the maintainability of our code. The main reason for this is that we only need to manage the contents of a record in the place it is declared. Therefore, we can change connections in our ports just by modifying the record type. If our design features multiple modules which use the same record, this can reduce the effort require to modify connections between entities.

• Declaring and Using a Record in VHDL

When we want to use a record in VHDL we must declare it as a type. We most commonly declare records inside a VHDL package . This allows us to use the record type in multiple different design files.

The code snippet below shows the general syntax we use to declare a record type in VHDL.

After we have declared a record type, we can use it in the exact same manner as any other port or signal in our VHDL design. We can assign data to individual elements in the record or to the entire array.

The code snippet below shows the two methods we can use to assign data to the record.

It is also possible for us to include records as elements in an array.

• An Example Record Type

Lets consider a basic example to better demonstrate how a record type works in VHDL. For this example, we will write a record which contains all the signals required in a UART interface.

The UART interface consists of 4 different signals. Each of these signals are a single bit which means we can use a std_logic type to model them.

The code snippet below shows how we would declare this record type.

After we have created the record, we can then use it in the type field for any port or signal in our VHDL design.

The code snippet below shows hows we would declare a signal which uses our UART record type.

Finally, we will obviously also want to drive data onto our record signal. The VHDL code snippet below gives some examples of how we can assign data to the record.

Write some VHDL code which creates an enumerated type for an FSM. The FSM has 4 states – idle, running, stopped and error

Create an integer subtype which can have a value between 5 and 200.

Write some VHDL code which declares an array of 8 32-bit std_logic_vectors

Write a record type which consists of an 8 bit unsigned type, a std_logic type and an unconstrained integer.

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Data Types in VHDL

In this article, we shall discuss data types in VHDL. After reading this article, you’ll be able to answer the following questions.

What are data types?

Data types are just attributes attached to the data that helps the VHDL compiler in understanding how to treat that particular data. In simpler words, these are special commands that tell the VHDL compiler what something is and what it is supposed to do next.

In VHDL, we define datatypes while initializing signals, variables, constants, and generics.

User-defined data types can be defined in a separate file and shared as a library. You can define a bunch of custom data types and put them in a library and use that whenever you want. Sort of like your personal toolkit!

Due to its usefulness, it is the most popular and widely used library in VHDL. It has useful datatypes like std_logic and std_ulogic which helps us to make simulation much more practical. And to make our VHDL programming easy, we use IEEE’s library and its functions quite often.

Significance of datatypes

Similarly, we store data values in variables of a suitable type. And the same analogy continues for other data objects like signals, constants, etc.

Consider a ‘signal Q’ whose datatype we don’t know yet. It is initialized with a value ‘0’. If we wish to change its value to ‘1’ later on. How we’ll do it?

As a programmer, you have the freedom to use a data type, but you should also utilize your wisdom to choose a suitable one.

Data types in the standard library

There are many data types defined in the standard library of VHDL. To make them easy to understand, we categorize them into the following four types:

Enumerated type

These datatypes can take several values listed/ enumerated in the standard library. Enumerated data types consist of the following types:

Boolean data type

A Boolean type data object can have a single value. Either ‘FALSE’ or ‘TRUE.’ That’s it. The logical operations that can be performed on Boolean variables are “and, or, not, nand, nor, xor.”

Initializing a Boolean variable and a signal with an initial value:

Bit data type

A Bit type of data object can either have ‘0’ or ‘1’. The logical operations that can be performed on Bit variables are the same as of Boolean, i.e. “and, or, not, nand, nor, xor.”

Initializing a Bit type variable and a signal without an initial value:

Character data type

A character type data object can hold any one character or special character at a time or can hold sum defined literal like NUL, SOX, STX, etc.

Initializing a character variable with an initial character:

All possible enumeration for a character data type

Severity levels.

So default value for data objects of datatype bit is ‘0’. And the same goes for all data types as mentioned in the table below

Numeric type

As the name suggests, these data types can hold numeric values only. Numeric data type consists of the following types:

Integer data type

Now, what are subtypes you ask, in short, a subtype is a datatype which has constrained values of its base type. Sound confusing?

Initialising a natural variable

Real data type

It can hold floating-point numbers ranging from -1.0E38 to +1.0E38. These are very helpful for precise calculation. For example, if we need to use the value of pi (π) for some calculations, then we can’t use an integer to store its value (3.14159). An integer can only store 3, which decreases preciseness of calculations. But a real can store floating digits of up to 6 decimal places.

Array data types

Bit vector -A bit_vector is simply an array of grouped bits, they are useful while defining multiple pin inputs. Consider an example. You are creating a 4-bit adder so you’ll need 4-bit inputs, rather than defining them individually you can use:

The statement above assigns ‘0’ to input(0), ‘1’ to input(1), and so on.

Miscellaneous

There are two data types in the standard library, i.e., ‘TIME.’ This is used to store values that can be further utilized for timing operation, like creating specific delays. Some units of time are also defined in the standard library, as shown below:

Initializing a time variable with an initial value

Data types from non-standard libraries

We use it to represent much more practical details of digital signals in circuits and wires.

'H' : This signal is also weak but it should probably go to 1

'-' : Don’t care.

Initializing a Std_ulogic  type variable and a signal with an initial value-

std_logic – This datatype has the same enumeration as of std_ulogic . However, the difference is that std_logic is resolved and we don’t need extra resolution function.

'1' : logic 1

'L' : This signal is also weak that it should probably go to 0

Initializing a Std_logic type variable and a signal with an initial value:

Std_ulogic_vector  – A mentioned earlier, an array is a collection of objects of the same type. So here also when we want to initialize a multi-bit input, we use vector notation to create a vector of multiple std_ulogic bits.

In the code above, we have created a record named ‘MODULE,’ and it has 4 data objects inside it. Now MODULE is a datatype in itself.

NO_OF_INPUTS of type BIT .

The above line of code assigns “50” to SIZE, “20 ns” to DELAY, “3” to NO_OF_INPUTS, and “2” to NO_OF_OUTPUTS.

Bit and bit_vector

In the above code, three ports are initialized, two inputs, and one output. For data input in 2×1 mux, we need 2-bit input we may use two different bits as

To assign values to both will take two lines of code as

This creates 2-bit input as input(0) and input(1) and assigning values to them is way more comfortable as

As always, if you have any queries, we would love to address them. Just drop in a comment in the comments section below.

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Understanding VHDL

Table of contents, 1. vhdl hardware description language, 2. design styles, 3. vhdl abstraction levels, 4. structure of vhdl modules, 5. vhdl data types, 6. vhdl variables, signals, constants, 7. vhdl operators, basics, structure, data types and operators.

Hardware description languages (HDL) are used to design digital and electronic systems. Today, the languages most widely employed are VHDL and Verilog. These description languages allow the user to write a program that describes the behavior of the circuit. This program can be used to simulate the operation of the circuit. And its implementation can be synthesized in a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or an Application Specific Integrated Circuit (ASIC).

VHDL stands for Very High-Speed Integrated Circuit Hardware Description Language and is what its name implies: a hardware description language. It is based on the ADA software programming language; the syntax is similar, but the way it behaves is different. VHDL models, describes, and simulates digital or electronic circuits and systems. Although VHDL and sequential programming languages (e.g., C / C++) look similar, VHDL handles sequential and concurrent executions. It also incorporates timing specifications (gate delays). Using an Electronic Design Automation (EDA) tool, a high-level VHDL behavioral model can be translated into a gate level netlist which describes the circuit in terms of gates and connections between them. The netlist is placed and routed to generate a layout. This layout created by the EDA tools is sometimes used to produce the electronic systems.

VHDL has many advantages:

• it supports design methodologies like top-down and bottom-up approaches,
• it provides a flexible design language,
• it allows a detailed implementation and a better design management,
• it has support for multi-level abstraction,
• it strongly supports code reusability and sharing.

Hardware description languages use two design methods: bottom-up or top-down. Nowadays, a hardware design uses both methodologies to implement a structure. In a top-down design approach, the designer adds details as the design progresses. First, he defines the top-level block and moves down to the smallest elements. Like a tree, the design starts from the roots (top-level block) and adds branches with the sub-blocks necessary to build the top-level.

The bottom-up methodology uses the smallest details to build the blocks, after which these blocks are used to create larger blocks. Thus, the top-level is built using blocks that are getting more and more abstract as the code is added. Top-down and bottom-up workflows are frequently combined. The top-level block's parameters are determined by the design architects. Logic developers divide the functionality into blocks and sub-blocks to determine how the design should be organized. Circuit designers are creating optimized circuits leaf-level cells. These leaf cells are then used to create higher-level cells. The logic-level designers start to design from the top and move down until all modules are defined in terms of leaf cells. The flow meets at this intermediate point, where the switch-level circuit designers have created a library of leaf cells using switches.

When discussing the various levels of abstraction in VHDL, it is all about the different styles of description. Thus, there are 3 major levels: behavioral, structural, and dataflow.

At this level, the model is represented by a functional description and is employed at the beginning of a design to be able to run a simulation. It is used mostly in test-bench design, because in the test-bench phase it is not so relevant if the hardware is achievable. Compared to other levels, behavioral is considered the highest abstraction level. At this level, a system is described in an algorithmic mode and does not imply a gate-level implementation. The behavioral level comprises one or more process statements, and each contains one or more sequential statements. In a simulator, all the statements are executed sequentially, similar to a conventional programming language.

Behavioral modeling uses sequential statements to describe a behavior of an entity. This makes it very similar to high-level programming languages, like C, C++, or JAVA. “Process” statements and various sequential statements are used to write this behavioral model. In VHDL, the descriptions of all processes are executed concurrently, but the statements included in the process description are executed sequentially.

A process label is just a name for a particular process. Assigning labels is especially useful while writing large pieces of code. They are not required, and their absence will not create any errors. A so called “sensitivity list” identifies all the signals by their name that the process is sensitive to. This list is optional, but without it, a process will run forever, unless a wait statement is included at the end of a process.

Example: 2-to-1 Multiplexer in behavioral modeling style.

The mode of operation of the multiplexer is declared in the architectural body, where the multiplexer sends the input signal from the user-specified address to its output. For the process to work properly, it must monitor the input ports. For this reason, the sensitivity list contains all three ports. Using IF … ELSIF statements, the multiplexer functionality can be created, and all these statements are running sequentially.

VHDL structural modeling is similar to doing a schematic design, but it uses text instead of block diagrams elements. This type of modeling has several advantages when it comes to large and complicated projects. Using a structural style, a big project can be split into two or more simple designs to make it easier to handle the complexity of the project. This allows to pack low-level functionality into modules. This way, already implemented modules can be reused without having to rewrite the design from scratch. In order to use this level of abstraction, one or more components need to be instantiated inside a design. For this, one or more architecture declarations need to be created. An architecture contains two parts, the declarative part and the statement section. In the declarative part, a component is declared with the ports that it uses. The statement section describes the way the ports interact with each other.

Example: 2 gates, AND & OR, connected in series

In this code, the output of an AND2 gate is linked to one of the inputs of an OR2 gate and compared with another signal.

VHDL dataflow modeling follows the way the data flows through the design, from input to output. This abstraction level specifies the functionality of a design without specifying its structure. This involves the description at a gate level of the appropriate logic gates (AND, OR, XOR, etc.). The dataflow uses one or more signal assignment statements. They can be used sequentially or in parallel. For this level, sequential designs are used, the output depends on the input and the previous states. Therefore, “memories” need to be used for the system designs.

For this abstraction level, several ways to implement a design are possible:

• concurrent signal assignments,
• conditional signal assignments,
• selected signal assignments.

For example, a multiplexer is a combinational circuit that selects, based on selection lines, one out of several inputs and sends it directly to the output. The table illustrates the truth table for a 4×1 multiplexer. Here, the Y column is the output with the selected port.

Example: Multiplexer using conditional signal assignment

Example: Multiplexer using selected signal assignment

VHDL Libraries and Packages

Libraries are a collection of packages that define the operators and operations in the logic utilized to describe a digital system. The IEEE library is commonly used; it defines a binary representation consisting of values of 0 and 1, and a standard logic representation (std_logic) with nine distinct logic values, of which the most important are: 0, 1, X (unknown) and Z (high impedance). To include a library in VHDL, the reserved word library is used in an instruction of this form:

Packages are a collection of elements, like data types, subprograms, constants, or operators, within a library. The reserved word for the inclusion of a package from a library is use, the instruction is written as:

For the IEEE library, to use the logic primitive’s description, it is required to include the package IEEE.std_logic_1164. For this, write the following code sequence:

VHDL Modules

The declaration for interface-signal uses this form:

• mode – indicates the direction of the signal: in, out, inout, buffer.
• in – carries information into the module, can be read but not updated in the module
• out – carries information out of the module, can be updated but not be read inside a module
• inout – can be read and updated, this mode is bidirectional
• buffer – carries information out of a module, and can be both updated and read from the module
• type – indicates the signal type: bit, boolean, std_logic, integer, real, character, time
• optional : a default value

For example, the next lines of code are the declaration for the entity of an and-gate with two inputs and one output:

The architecture descriptor – architecture – describes the function of the digital circuit. In this part of a module, one or more abstraction level presented above are combined to create an architecture. The code can set out how the circuit behaves using functional blocks and the connection between them, or a mathematical description of the logical functions (truth table, transition diagram, algorithm). The declaration of an architecture uses this form:

In the declaration, the signals and constants are assigned if they are needed. To describe logical primitives, the body of VHDL module architectures consists of:

• assignment operators:
• fundamental logic operators (not, and, or, nand, nor, xor, xnor)

Example: The and-gate architecture with two inputs described with fundamental logic and is:

VHDL Module Instantiation

Module instantiation is used to connect circuit elements. At the top level, the connection is made between modules, and the EDA tool creates the netlist for all the components and connections that are used. A VHDL design description written exclusively with component instantiation is known as “Structural VHDL”. This method is very similar to the schematic entry; in this case, instead of using graphic elements, it is implemented as text. One or more components can be declared in the architecture body. To instantiate a component inside a design, the following two steps are needed:

• declare the components in the declarative part of the architecture, and
• instantiate the component in the architecture statement section.

The declaration section of the architecture is included between the keyword “is” and “begin”:

For example, to instantiate the and-gate with two outputs modules in another architectural model, the simplest way is to copy the entity of and2 and paste it to the architectural body. After that, change the “entity” to “component”.

• Predefined data types:

* users defined data, for example, enumeration:

VHDL is a strongly typed language, so different data types cannot be combined in the same instruction.

Vector Types

When designing with a hardware description language, data buses are often used. Data buses comprise multiple bit buses. The data types presented above allow single bits to be modeled in a design. A vector consists of one or more bits that are modeled similarly to one of the predefined data. The most basic and encountered types of vectors in VHDL are made up of several bit or std_logic types. The code below is an example of how to declare a vector type signal in VHDL.

The [ range ] field is used to determine the number of bits in the vector and the location of the most significant and least significant bits. The key word used to describe the range value in VHDL are: downto and to. The next lines present a declaration of an 8-bit vector using the keywords:

Conversion Type

When writing VHDL code, it is often necessary to do a data conversion. Two general methods to convert between data types are available. The first method is to cast the signal to the correct type. In this method, it is converted between the signed, unsigned and std_logic_vector.

The code below is an example demonstrating the syntax to cast signals or data.

The second way employs functions. This method is used to convert between the signed or unsigned types and the integer type. To use a suitable conversion function, it is needed to include either the numeric_std or the std_logicarith packages. These packages are available in the IEEE library.

Assigning Data Values

When assigning data to a vector type, VHDL uses quotation marks (“) instead of apostrophes. Also, it can specify to use a hexadecimal notation by adding an ‘x’ to the start of the data. This works if the number of bits is a factor of four. Using octal values can be done by adding an ‘o’ to the start of the data. This works only with VHDL-2008. The code below gives some examples of how to assign data to vector types in VHDL.

Because VHDL is similar to other programming languages, it allows variables. These are declared in the architecture declaration area.

• variable – receives a value that can be updated during running simulations
• signal – time-dependent size that maps to ports
• constant – receives a value that cannot be modfied during simulation

Example: In this example, several variables of each of the above types are declared and used in a small code combination:

VHDL has a set of operators that can be used in creating designs. Predefined operators:

Example 1: After declaring the variables, f is assigned the value between a and b using a binary operator. The binary operator “and” can be replaced with another binary operator according to the designer's need. This operation is performed after the delay; for this task, the timing operator “after” is used.

Example 2: Uses the timing operator “wait” to implement a breakpoint and wait for an event specified to happen:

Example 3: Uses different shift operators to make changes at a bit level.

Example 4: The combined use of several operators:

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courses:system_design:vhdl_language_and_syntax:data_types

Fundamentals

• Every signal has a type
• Type specifies possible values
• Types has to be defined at signal declaration …
• entity: port declaration, or in
• architecture: signal declaration
• Types have to match

In VHDL, signals must have a data type associated with them that limits the number of possible values. This type has to be fixed when the signal is declared, either as entity port or an internal architecture signal, and can not be changed during runtime. Whenever signal values are updated, the data types on both sides of the assignment operator ’⇐’ have to match.

Standard Data Types

• Every type has a number of possible values
• Standard types are defined by the language
• User can define his own types

A number of data types are already defined in the standard package which is always implicitly referenced.

’ boolean ’ is usually used to control the flow of the VHDL execution while ‘ bit ’ uses level values (’ 0 ’, ’ 1 ’) instead of truth values (’ false ’, ’ true ’) and is therefore better suited to model wires. Number values can be communicated via signals of type ’ integer ’ or ’ real ’.

The actual range and accuracy depends on the platform implementation and only lower bounds are defined, e.g. integers are guaranteed to be at least 32 bits wide. Floating point operations can not be synthesized automatically, yet, i.e. the use of ’ real ’ data types is restricted to testbench applications.

The same applies to ’ character ’ and ’ time ’.

Real types are not synthesizeable:

• You have to decide how many bits will be used for the digits pre and after the decimal point!
• you have to use synthesizeable division algorithms to calculate them

Data type ‘time’

• Testbenches
• Gate delays
• Multiplied/divided by integer/real
• Returns TIME type
• Internally in smallest unit (fs)
• Available time units 
fs, ps, ns, us, ms, sec, min, hr

’ time ’ is a special data type as it consists out of a numerical value and a physical unit.

It is used to delay the execution of statements for a certain amount of time, e.g. in testbenches or to model gate and propagation delays. Signals of data type ’ time ’ can be multiplied or divided by ’ integer ’ and ’ real ’ values. The result of these operations remains of data type ’ time ’.

The internal resolution of VHDL simulators is set to femto-seconds (fs).

Definition of Arrays

• Collection of signals of the same type
• bit_vector (array of bit)
• string (array of character)
• Unconstrained arrays: definition of actual size during signal/port declaration

Arrays are useful to group signals of the same type and meaning.

Two unconstrained array data types, i.e. whose range is not limited, are predefined in VHDL:

• ’ bit_vector ’ and ’ string ’ are arrays of ’ bit ’ and ’ character ’ values, respectively.

Please note that the array boundaries have to be fixed during signal declarations, e.g. ’bit_vector(3 downto 0)’.

Only constrained arrays may be used as entity ports or architecture signals.

‘integer’ and ‘bit’ Types

• Example for using ‘bit’ and ‘integer’

Integer signals will be mapped to a number of wires during synthesis.

These wires could be modelled via bit vectors as well, yet ’ bit_vector ’ signals do not have a numerical interpretation associated with them.

Therefore the synthesis result for the two example architectures would be the same. The process models a simple multiplexer which selects the input A as source for its output Z when the select signal SEL is ’1’ and the input B otherwise.

Please note that the multiplexer process is exactly the same for both data types!

Assignments with Array Types

• Z_BUS(3) ⇐ C_BUS(0)
• Z_BUS(2) ⇐ C_BUS(1)
• Z_BUS(1) ⇐ C_BUS(2)
• Z_BUS(0) ⇐ C_BUS(3)

Special care is necessary when signal assignments with arrays are carried out.

Although the data type and the width of the signals have to match, this is not true for the order of the array elements.

The values are assigned according to their position within the array, not according to their index.

Therefore it is highly recommended to use only one direction (usually ’ downto ’ in hardware applications) throughout your designs.

Bit String Literals

• Single bit values are enclosed in '.'
• optional base specification (default: binary)
• Values may be separated by underscores to improve readability

The specification of signal values is different for the base types ’character’ and ’bit’ and their corresponding array types ’string’ and ’bit_vector’. Single values are always enclosed in single quotation marks (’), while double quotation marks (“) are used to specify array values.

As bit vectors are often used to represent numerical values, VHDL offers several possibilities to increase the readability of bit vector assignments.

First, a base for the following number may be specified. Per default binary data consisting of ’0’s and ’1’s is assumed. Please note that the values have to enclosed in double quotation marks even though only a single symbol might be necessary when another base is used! Additionally, underscores (_) may be inserted at will to split long chains of numbers into smaller groups in order to improve readability.

Since VHDL’93, the same rules apply to the enhanced bit vector types ’ std_(u)logic_vector ’, which will be discussed later on, as well.

Concatenation

Concatenation operator: &

Resulting signal assignment:

• BYTE(7) ⇐ A_BUS(3)
• BYTE(6) ⇐ A_BUS(2)
• BYTE(5) ⇐ A_BUS(1)
• BYTE(4) ⇐ A_BUS(0)
• BYTE(3) ⇐ B_BUS(3)
• BYTE(2) ⇐ B_BUS(2)
• BYTE(1) ⇐ B_BUS(1)
• BYTE(0) ⇐ B_BUS(0)
• Z_BUS(3) ⇐ A_BIT
• Z_BUS(2) ⇐ B_BIT
• Z_BUS(1) ⇐ C_BIT
• Z_BUS(0) ⇐ D_BIT

As signal assignments require matching data types on both sides of the operator it is sometimes necessary to assemble an array in the VHDL code.

The concatenation operator ’ & ’ groups together the elements on its sides which have to be of the same data type, only.

Again, the array indices are ignored and only the position of the elements within the arrays is used. The concatenation operator may be used on the right side of signal assignments, only!

• Aggregates bundle signals together
• May be used on both sides of an assignment
• Keyword ‘other’ selects all remaining elements

Another way of assigning signals which does not suffer from this limitation is via the aggregate construct.

Here, the signals that are to build the final array are enclosed in a ’(’ ’)’ pair and separated by ’,’.

Instead of a simple concatenation, it is also possible to address the array elements explicitly by their corresponding index, as shown in the last signal assignment statement of the aggregate example.

The keyword ’ others ’ may be used to select those indices that have not been addressed, yet.

Slices of Array

• Slices select elements of arrays

The inverse operation of concatenation and aggregation is the selection of slices of arrays, i.e. only a part of an array is to be used.

The range of the desired array slice is specified in brackets and must match the range declaration of the signal!

Of course, it is possible to select only single array elements.

Chapters of System Design > VHDL Language and Syntax

• General Issues
• VHDL Structural Elements
• Process Execution
• Extended Data Types
• Sequential Statements
• Subprograms
• Subprogram Declaration and Overloading
• Concurrent Statements

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Signal assignment type

What is the meaning of "combinational assignment" and "registered assignment" to signals? In particular what are the differences between these two types of assignments?

• state-machines

2 Answers 2

Essentially, the difference boils down to whether the signal gets assigned on a clock edge or not.

Combinational code, like A <= B + 1 would have A being assigned B+1 "immediately," whereas

would result in A being assigned B+1 only on a rising clock edge. With code like this, other blocks can use the value of A being guaranteed that its value will be stable and unchanging after a clock edge.

Registers, or clock gating in general I suppose, are really what make designs of any complication possible. You create a pipeline of operations by putting a register at the border between operations. For example, the input operands to an ALU must be stable - in a register- so that the ALU can execute properly, and the result of the ALU's execution should be in a register so that whatever block uses it does not 'see' the changing values inside the ALU as the calculations take place, but only the stable last result.

• \$\begingroup\$ Question: Is a transparent latch considered combinatorial or registered? \$\endgroup\$ –  The Photon Commented May 14, 2012 at 4:52
• \$\begingroup\$ Yes and no - the input to a transparent latch propagates directly to the output, not on a clock edge. But the addition of an enable signal could make the latch be controlled on a clock edge, ie, opaque. \$\endgroup\$ –  Kevin H Commented May 14, 2012 at 16:17

Assignments in VHDL are neighter specified as registered or combinatorial. In VHDL the actual assignment type (the type of RTL logic generated) is just inferred.

Registers in VHDL are created explicitly by assigning a signal on a clock edge, though just because a process has a clock it does not mean all signals in that block will be assigned on every edge.

Also registers can be inferred without a clock, if some path through a process does not assign a signal, then VHDL assumes you meant to latch that signal between successive passes. This is called an inferred latch (and should be avoided).

VHDL does not know about the technology that you are going to be using. It does not know whether your synthisis engine can generate T,D,JK,SR, or any other sort of latch. For that reason it just suggests a latch, it is up to the synthisis enging to decide which latch fits the bill or if it is simply impossible. Similarlay the fitter might say that a particular latch requested by the synthisis enging is not available or there are no enough of them.

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Assignment Symbol in VHDL

VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols:

Either of these assignment statements can be said out loud as the word “gets”. So for example in the assignment: test <= input_1; You could say out loud, “The signal test gets (assigned the value from) input_1.”

Note that there is an additional symbol used for component instantiations (=>) this is separate from an assignment.

Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator , otherwise it’s an assignment.

One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is good practice to assign all signals in an FPGA to a known-value when the FPGA is initialized. You should avoid using a reset signal to initialize your FPGA , instead use the := signal assignment.

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Designing Circuits with VHDL

1. introduction, 2. combinational circuits, signal assignments in vhdl.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullAdder is     port(  A,B: in  std_logic;  -- input bits for this stage            Ci:   in  std_logic; -- carry into this stage            S:    out std_logic; -- sum bit            Co:   out std_logic  -- carry out of this stage     ); end fullAdder; architecture a1 of fullAdder is begin     S <= A xor B xor Ci;     Co <= (A and B) or ((A xor B) and Ci); end a1;

Processes and Conditional Statements

if a = '0' then     x <= a;     y <= b; elsif a = b then     x <= '0';   y <= '1'; else     x <= not b; y <= not b; end if;

Every signal that is assigned a value inside a process must be defined for all possible conditions.

Case Statements

Structural vhdl, 3. sequential circuits.

busy   is high when the circuit is in the middle of performing an operation;             while busy is high, the insert and delete inputs are ignored; the             outputs are not required to have the correct values when busy is high empty     is high when there are no pairs stored in the priority queue; delete             operations are ignored in this case full      is high when there is no room for any additional pairs to be stored;             insert operations are ignored in this case

• For adjacent pairs in the bottom row, the pair to the left has a key that is less than or equal to that of the pair on the right.
• For pairs that are in the same column, the key of the pair in the bottom row is less than or equal to that of the pair in the top row.
• In both rows, the empty blocks (those with dp =0) are to the right and either both rows have the same number of empty blocks or the top row has one more than the bottom row.

entity priQueue is     Port (clk, reset : in std_logic;           insert, delete : in std_logic;           key, value : in std_logic_vector(wordSize-1 downto 0);           smallValue : out std_logic_vector(wordSize-1 downto 0);           busy, empty, full : out std_logic     );    end priQueue; architecture a1 of priQueue is constant rowSize: integer := 4; -- local constant declaration type pqElement is record     dp: std_logic;     key: std_logic_vector(wordSize-1 downto 0);     value: std_logic_vector(wordSize-1 downto 0); end record pqElement; type rowTyp is array(0 to rowSize-1) of pqElement; signal top, bot: rowTyp; type state_type is (ready, inserting, deleting); signal state: state_type; begin     process(clk) begin         if rising_edge(clk) then             if reset = '1' then                 for i in 0 to rowSize-1 loop                     top(i).dp <= '0'; bot(i).dp <= '0';                 end loop;                 state <= ready;             elsif state = ready and insert = '1' then                 if top(rowSize-1).dp /= '1' then                     for i in 1 to rowSize-1 loop                         top(i) <= top(i-1);                     end loop;                     top(0) <= ('1',key,value);                     state <= inserting;                 end if;             elsif state = ready and delete = '1' then                 if bot(0).dp /= '0' then                     for i in 0 to rowSize-2 loop                         bot(i) <= bot(i+1);                     end loop;                     bot(rowSize-1).dp <= '0';                     state <= deleting;                 end if;             elsif state = inserting or state = deleting then                 for i in 0 to rowSize-1 loop                     if top(i).dp = '1' and                         (top(i).key < bot(i).key                          or bot(i).dp = '0') then                         bot(i) <= top(i); top(i) <= bot(i);                     end if;                end loop;                 state <= ready;             end if;         end if;     end process;     smallValue <= bot(0).value when bot(0).dp = '1' else                   (others => '0');     empty <= not bot(0).dp;     full <= top(rowSize-1).dp;     busy <= '1' when state /= ready else '0'; end a1;

4. Functions and Procedures

package commonConstants is     constant lgWordSize: integer := 4;        constant wordSize: integer := 2**lgWordSize; end package commonConstants; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commonConstants.all; entity firstOne is     Port (a: in std_logic_vector(0 to wordSize-1);           x: out std_logic_vector (lgWordSize downto 0)      ); end firstOne; architecture a1 of firstOne is procedure encode(x: in std_logic_vector(0 to wordSize-1);                 indx: out std_logic_vector(lgWordSize-1 downto 0);                 errFlag: out std_logic) is -- Unary to binary encoder. -- Input x is assumed to have at most a single 1 bit. -- Indx is equal to the index of the bit that is set. -- If no bits are set, errFlag bit is made high. -- This is conceptually simple. -- --        indx(0) is OR of x(1),x(3),x(5), ... --        indx(1) is OR of x(2),x(3), x(6),x(7), x(10),x(11), ... --        indx(2) is OR of x(4),x(5),x(6),x(7), x(12),x(13),x(14(,x(15),... -- -- but it's tricky to code so it works for different word sizes. type vec is array(0 to lgWordSize-1) of std_logic_vector(0 to (wordSize/2)-1); variable fOne: vec; variable anyOne: std_logic_vector(0 to wordSize-1); begin     -- fOne(0)(j) is OR of first j bits in x1,x3,x5,...     -- fOne(1)(j) is OR of first j bits in x2,x3, x6,x7, x10,x11,...     -- fOne(2)(j) is OR of first j bits in x4,x5,x6,x7, x12,x13,x14,x15,...     for i in 0 to lgWordSize-1 loop         for j in 0 to (wordSize/(2**(i+1)))-1 loop                        for h in 0 to (2**i)-1 loop                 if j = 0 and h = 0 then                     fOne(i)(0) := x(2**i);                 else                     fOne(i)((2**i)*j+h) := fOne(i)((2**i)*j+h-1) or                                            x(((2**i)*(2*j+1))+h);                 end if;             end loop;         end loop;         indx(i) := fOne(i)((wordSize/2)-1);     end loop;     anyOne(0) := x(0);     for i in 1 to wordSize-1 loop         anyOne(i) := anyOne(i-1) or x(i);     end loop;     errFlag := not anyOne(wordSize-1); end procedure encode; function firstOne(x: std_logic_vector(0 to wordSize-1))                         return std_logic_vector is -- Returns the index of the first 1 in bit string x. -- If there are no 1's in x, the value returned has a -- 1 in the high order bit. variable allZero: std_logic_vector(0 to wordSize-1); variable fOne: std_logic_vector(0 to wordSize-1); variable rslt: std_logic_vector(lgWordSize downto 0); begin     allZero(0) := not x(0);     fOne(0) := x(0);     for i in 1 to wordSize-1 loop         allZero(i) := (not x(i)) and allZero(i-1);         fOne(i) := x(i) and allZero(i-1);     end loop;     encode(fOne,rslt(lgWordSize-1 downto 0),rslt(lgWordSize));     return rslt; end function firstOne; begin     x <= firstOne(a); end a1;

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VHDL assignment to an array type

Consider a type

Why do I get a compiler error when I try to create a constant value of this type, for example. Note that I have only tried using Altera's Quartus II.

Error: VHDL Type mismatch error at [filename.vhd](line number): cFoo type does not match string literal.

However everything is ok if my type is

with an example assignment to a constant of:

Moreover consider that I try to assign index 0 with another constant. For example.

To which the error the compiler spits out is now:

VHDL error at [filename.vhd](line number): type of identifier "cBar" does not agree with its usage as "foo" type.

So basically its telling me that the compiler does not realize that the assignment is to the index of 0 but instead an assignment to the the array type.

How can I let the compiler know that the assignment is to only index 0?

• variable-assignment

IEEE Std 1076 9.3.3 Aggregates, 9.3.3.1 para 4:

Both named and positional associations can be used in the same aggregate, with all positional associations appearing first (in textual order) and all named associations appearing next (in any order, except that it is an error if any associations follow an others association). Aggregates containing a single element association shall always be specified using named association in order to distinguish them from parenthesized expressions.

With an MCVE :

You need to use named association with a single element. The first example specifies index 0, the second any elements.

Para 3 of the above quoted subsection:

Each element association associates an expression with elements (possibly none). An element association is said to be named if the elements are specified explicitly by choices; otherwise, it is said to be positional. For a positional association, each element is implicitly specified by position in the textual order of the elements in the corresponding type declaration.

It's helpful to see the BNF:

aggregate ::= ( element_association { , element_association } ) element_association ::=      [ choices => ] expression choices ::= choice { | choice } choice ::=      simple_expression      | discrete_range      | element _simple_name      | others

• Champion. Thank you for filling the gap in my understanding. –  CJC Commented Jul 4, 2016 at 12:19

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